ASR vs ASL and sign bit

[Circlotron]

If we do an ASR the sign bit remains unchanged, but if we do an ASL (same as LSL) the sign bit gets overwritten. Why is this allowed/meant to happen?

[helius]

If you left shift a data word so that it overflows, the result is inevitably wrong. Whether it has the right sign or not is a rather moot point.
Many ISAs do not have separate opcodes for logical and arithmetic left shift. This means that there are 3 shift opcodes.

[Circlotron]

If you left shift a data word so that it overflows, the result is inevitably wrong.

True, but if the sign bit got pushed into the carry bit you could deal with it. But if the sign bit is trashed even when there is no overflow...
Talking about 'HC908 BTW.

[JS]

If you left shift a data word so that it overflows, the result is inevitably wrong.

True, but if the sign bit got pushed into the carry bit you could deal with it. But if the sign bit is trashed even when there is no overflow...
Talking about 'HC908 BTW.

Check it before!?

JS

[helius]

True, but if the sign bit got pushed into the carry bit you could deal with it. But if the sign bit is trashed even when there is no overflow...

If the sign bit changes as the result of a left shift, it is an overflow by definition.
The instruction table (Table 8-1) of the 68HC908 data sheet is not completely helpful in this regard:
Its entry for ASR (arithmetic shift right) shows the V (overflow) bit and N (negative) bit as being set or reset according to the result, but arithmetic right shift never overflows (the sign bit always remains the same). So the V bit should say 0 (always reset) and the N bit should say - (never changed). This makes the difference between ASR and ASL clearer.

[Circlotron]

Actually I think I’m starting to get it now. Left shifting anything greater than -63 will cause an overflow.

 -63 or less will have msb (bit 6) as 1 so after left shift it will then occupy bit 7 position and look like a sign bit. I think...

[hamster_nz]

... and don't forget, ASR is not the same as divide by 2!

[newbrain]

... and don't forget, ASR is not the same as divide by 2!

I se that as divide by two, with rounding towards the lowest value (not the lower absolute value).
IIRC, it's specified like that in ANSI forth, but cannot check now.

EtA: This is one of the things that changed between C89 and C99, in the former standard the result was implementation defined, so an asr could well be the implementation for /2, in the latter rounding towards 0 is specified.

[brucehoult]

... and don't forget, ASR is not the same as divide by 2!

It's close.

You can follow the C standard correctly by adding 1 before shifting, if and only if the number is negative. In other words, unconditionally add the sign (leftmost bit).

On a machine like RISC-V with fast large shifts but no condition codes you can do it like:

Code: [Select]

srli tmp,x,63
add x,x,tmp
srai x,x,1

On a machine with slow or only single bit shift, but with condition codes you can do it like:

Code: [Select]

lsl tmp,x,1
adc x,x,0
asr x,x,1

If you've only got a single accumulator, e.g. 6502, then you need to juggle a little:

Code: [Select]

tax
asl a
txa
adc #0
asr a

gcc on x86_64 chooses the first method even though it has a carry flag.

Any of these is going to be massively faster than doing a real divide, even if it's not just a single instruction.

[NorthGuy]

If you've only got a single accumulator, e.g. 6502, then you need to juggle a little:

It depends on the CPU. For example, PIC16 has a single accumulator, but you don't need to juggle

Code: [Select]

btfsc a,7
incf a,f
asrf a,f


[JPortici]

mm..
PIC16 base/midrange core (PIC16Fxxx) doesn't have any arithmetic shift.. it only has RRF/RLF, ROTATE through carry.
PIC16 enhanced midrange core (PIC16F1xxx) does have arithmetic right shift (ASRF), which preserves the MSB.. and it also has LSLF/LSRF
Strange enough, PIC18 doesn't have shift instructions instead, only rotate instructions

[NorthGuy]

PIC16 base/midrange core (PIC16Fxxx) doesn't have any arithmetic shift.. it only has RRF/RLF, ROTATE through carry.

These don't have any shifts at all, so you would have to manufacture ASR and bust WREG:

Code: [Select]

rlf a,w
rrf a,f


Strange enough, PIC18 doesn't have shift instructions instead, only rotate instructions

Microchip design decisions are often ... strange   PIC18 is an example where Microchips didn't think well about many things.

[DJohn]

If you've only got a single accumulator, e.g. 6502, then you need to juggle a little:

Code: [Select]

tax
asl a
txa
adc #0
asr a


Sadly, the 6502 has no asr.  This is the best I can do:

Code: [Select]

cmp #128
adc #0
cmp #128
ror a


[brucehoult]

If you've only got a single accumulator, e.g. 6502, then you need to juggle a little:

Code: [Select]

tax
asl a
txa
adc #0
asr a


Sadly, the 6502 has no asr.  This is the best I can do:

Code: [Select]

cmp #128
adc #0
cmp #128
ror a


Oh, bugger, you're right! :-(  6800 has asr but its nephew the 6502 only has asl (where it doesn't matter) and lsr.

It's over 35 years since I actually programmed those in assembler.