Well, a couple of years ago I decided to get involved in CPLD's, I chose Atmel's range over XILINIX.Atmel supply you with a language called cupl and XILINIX supply you with ABEL they are very similair.Now it turns out XILINIX have discontinued the xc9536 and the xc9572 chips and they are not 5V but 3.3V. So, fortunately I chose Atmel, as all their parts range are still available at Mouser.
The thing is though, CUPL is very buggy making it's usage time comsuming, but if like me you put up with it and learn what you can do with it.Is there anybody here using cupl language?
Well, of course, CUPL was intended for PALs and GALs, where the devices were so simple that one could describe the functionality via simple combinational logic equations. Manual logic minimization via Karnaugh maps was very common. Very simple state machines could also be created. Like other posters said, if targeting CPLDs or FPGAs then I don't see any need to use CUPL. New tools are much more productive; Verilog supports low-level logic description via combinational statements but also higher-level behavioral language constructs, which gets more done in less time, no need to manually do logic minimizations because the tool does this automatically.
Important: CUPL also does not analyze timing automatically like modern tools. Concepts like Static Timing Analysis (STA) is vital to actually get any design working in an FPGA. Anything but the very simplest CPLD design should also use proper timing analysis.
Finally; I actually used CUPL about 10 years ago when I created the below dump-switch PCI card. Anything more complex than that project (i.e. CPLD) should use the CPLD vendor's modern toolset.
http://www.summitsoftconsulting.com/DumpSwitchCard.htm