Author Topic: ATMEL's CUPL language for their CPLD range of chips, what do you think.  (Read 15546 times)

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Offline commieTopic starter

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Well, a couple of years ago I decided to get involved in CPLD's, I chose Atmel's range over XILINIX.Atmel supply you with a language called cupl and XILINIX supply you with ABEL they are very similair.Now it turns out XILINIX have discontinued the xc9536 and the xc9572 chips and they are not 5V but 3.3V. So, fortunately I chose Atmel, as all their parts range are still available at Mouser.

The thing is though, CUPL is very buggy making it's usage time comsuming, but if like me you put up with it  and learn what you can do with it.Is there anybody here using cupl language? :popcorn:

 

Offline ataradov

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #1 on: October 06, 2015, 10:43:33 pm »
The only reason Atmel maintains FPGAs is contractual obligations. As soon as contracts expire, they will be gone in a jiffy.

Don't do any new designs using them.
Alex
 

Offline JoeN

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #2 on: October 07, 2015, 07:03:45 am »
The only reason Atmel maintains FPGAs is contractual obligations. As soon as contracts expire, they will be gone in a jiffy.

Don't do any new designs using them.

That's what I thought.  They seem to have about 0.0000001% of the market.  It looks like they have not introduced a new IC in about 10 years.  How did they get into this bind?
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Online xtech

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #3 on: October 07, 2015, 07:18:25 am »
XC95xx parts are 5V but XC95xxXL requires 3.3V (but inputs are 5V tollerant). Don't waste time for ABEL/CUPL, you can use VHDL what will be good if you are planning to switch in the future for FPGAs or larger CPLDs. I'm using also some old Lattice GALs - they are cheap and can be programmed in VHDL too (free IDE from Lattice). Programming GALs is a little problem - support in chinese programmers like TL866 is dubious (especially for GAL22V10, bigger are not supported) but the is always old good Galblast - requires old computer with 16-bit (I've not managed to run it on XP/7) but I've prepared USB bridge for Galblast hw with Arduino and simple command line app for 32-bit Windows.

XC95xx (not XL) are still available for low money on aliexpress for example (but in tqfp housings, good they are not refurbished like GAls there)
 

Online coppice

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #4 on: October 07, 2015, 07:29:18 am »
The only reason Atmel maintains FPGAs is contractual obligations. As soon as contracts expire, they will be gone in a jiffy.
Don't do any new designs using them.
That's what I thought.  They seem to have about 0.0000001% of the market.  It looks like they have not introduced a new IC in about 10 years.  How did they get into this bind?
Why do you see it as a bind? Markets change. You only get into a bind if you don't change with them.
 

Offline commieTopic starter

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #5 on: October 07, 2015, 10:04:03 am »
It looks like they have not introduced a new IC in about 10 years.

Question is, how do improve on the current range?, they are all flash programmable making them very flexible. The ATF1504 costs about £2.50 in qty of 25, however the ATF1508 (128 macrocell plcc68) jumps to a staggering £9.00 per chip and the plcc64 adapter, for my programmer, costs  a further £250.00.  :scared:
 

Offline ehughes

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #6 on: October 07, 2015, 12:26:09 pm »
CUPL and ABEL are both ancient.

All the real vendors use Verilog or VHDL.

The Atmel parts are an extreme dead end.

Look into Lattice and Microsemi as well.  They have some stuff at the CPLD end as well.

 
 

Offline Kalvin

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #7 on: October 07, 2015, 01:24:49 pm »
I would look at the small Flash-based FPGA devices. For example, you can get a small-size FPGA in less than $2:

http://hackaday.com/2015/07/03/hackaday-prize-entry-they-make-fpgas-that-small/

Digikey prices for different iCE40-series FPGAs:

http://www.digikey.com/product-search/en/integrated-circuits-ics/embedded-fpgas-field-programmable-gate-array/2556262?k=iCE40

No 5V tolerant I/O? Just add a cheap voltage level translator to each pin which requires 5V tolerant input or needs to be able to drive 5V output.
There are available cheap quad logic level translators which are bidirectional and can detect the direction automagically.
 

Offline ataradov

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #8 on: October 07, 2015, 03:33:31 pm »
How did they get into this bind?
It is normal to guarantee products for 9-12 years for general public and 20+ years for military and space industry.
Alex
 

Offline poorchava

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #9 on: October 07, 2015, 04:03:34 pm »
Add automotive to that - 20 years part availability contracts are a normal thing.

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Offline commieTopic starter

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #10 on: October 07, 2015, 04:36:10 pm »
Well, is Verilog or VHDL free to download or what? Take the industry standard devices like 16V8 and 22V10, does Lattice or any other vendor sell these two devices at reasonable price in a pdil20 and pdil24 footprint respectively and are they 5V operable?. If you answer no to my last question then I'm afraid Atmel fits my criteria for the time being. :popcorn:

« Last Edit: October 07, 2015, 04:51:51 pm by commie »
 

Offline ataradov

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #11 on: October 07, 2015, 04:40:51 pm »
For what chip? There is no generic Verilog or VHDL, all tools come only from a chip maker.
Alex
 

Offline commieTopic starter

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #12 on: October 07, 2015, 04:56:10 pm »
For what chip? There is no generic Verilog or VHDL, all tools come only from a chip maker.


Hmmmm....,I see, so once you have made your choice and learned their version of VHDL language, then you are locked in to the chip vendor, right?
 

Offline ataradov

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #13 on: October 07, 2015, 04:59:16 pm »
VHDL is common for all, but tools that can interpret VHDL and compile it down to a hardware configuration file are vendor specific, of course.
Alex
 

Offline westfw

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #14 on: October 07, 2015, 05:16:09 pm »
Quote
All the real vendors use Verilog or VHDL.
Even for small (GAL18v10-sized) PALs?   I didn't know you could do that!
 

Offline joeqsmith

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #15 on: October 07, 2015, 05:25:44 pm »
The thing is though, CUPL is very buggy making it's usage time comsuming, but if like me you put up with it  and learn what you can do with it.Is there anybody here using cupl language? :popcorn:

 |O |O |O

When PALASM stopped working with Windows NT, I tried CUPL.  At the time Logical Devices owned them.  It was a nightmare.   I switched to the Lattice tools.  They, like many others were using Synplify at the time for their synthesis tool.   

How many of you are still using a third party synthesis tool?  What about third party simulation tools?

Offline ataradov

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #16 on: October 07, 2015, 05:32:42 pm »
Even for small (GAL18v10-sized) PALs?   I didn't know you could do that!
I don't know much about very simple devices. There is no technical reason why you can't use VHDL, but I don't know if manufacturers bothered to implement it.

For simple devices it will basically be instantiation of the available blocks and manual connections between them. I doubt you could use actual code.
Alex
 

Offline commieTopic starter

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #17 on: October 07, 2015, 05:37:17 pm »
I would look at the small Flash-based FPGA devices. For example, you can get a small-size FPGA in less than $2:

Yes indeed you can but it is totally unusable in its single state, to use these devices you will need a chip vendors 'breakout' or evaluation board costing about $50.

There are already enough electronics technology to keep the feed going for the next 100 years, thing is the stack is growing ever larger with time so sooner or later something should filter through.I want pdil only.
 

Offline commieTopic starter

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #18 on: October 07, 2015, 05:44:31 pm »
I tried CUPL. It was a nightmare.     

Yep I agree, but free to download and use., but what else would you use to program a 16V8 or 22V10?
« Last Edit: October 07, 2015, 06:00:04 pm by commie »
 

Offline helius

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #19 on: October 07, 2015, 06:07:15 pm »
Even for small (GAL18v10-sized) PALs?   I didn't know you could do that!
I don't know much about very simple devices. There is no technical reason why you can't use VHDL, but I don't know if manufacturers bothered to implement it.

For simple devices it will basically be instantiation of the available blocks and manual connections between them. I doubt you could use actual code.
"Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 Verilog as its Hardware Description Languages (HDL) for design entry. Then, it synthesizes and optimizes the entered design, and outputs a JEDEC or Intel® hex file for the desired PLD or CPLD (see Figure 1)."

It appears to synthesize GAL configurations from behavioral architectures. Cypress sold it in the '90s.
« Last Edit: October 07, 2015, 06:12:45 pm by helius »
 

Offline Kalvin

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #20 on: October 07, 2015, 06:19:09 pm »
I would look at the small Flash-based FPGA devices. For example, you can get a small-size FPGA in less than $2:

Yes indeed you can but it is totally unusable in its single state, to use these devices you will need a chip vendors 'breakout' or evaluation board costing about $50.


Not necessarily, as there are open source tools and very inexpensive open-hardware development boards:

http://hackaday.com/2015/05/29/an-open-source-toolchain-for-ice40-fpgas/

I haven't used those tools, so I cannot say how mature those are and what devices are currently supported.

Actually, you do not need to buy chip vendor breakout boards or programmers, as quite a few cheap chinese programmers are available at eBay for different FPGA-devices. However, one needs to be vary careful that the cheap gadget is really compatible with the tools and the target FPGA device.

The Verilog and/or VHDL compilers are available for free from the FPGA device vendors.
« Last Edit: October 07, 2015, 06:21:41 pm by Kalvin »
 

Offline joeqsmith

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #21 on: October 07, 2015, 09:59:35 pm »
I tried CUPL. It was a nightmare.     

Yep I agree, but free to download and use., but what else would you use to program a 16V8 or 22V10?

Dang, when I got CUPL, it was a paid program.  PALASM was free.  But again, I switched to the Lattice tools which supported the 22V10.  I actually just did a design with a 22V10 for the fun of it.   DOSBOX had a problem with PALASM but I was able to get the old Lattice tools to work.   

Offline John_ITIC

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #22 on: October 07, 2015, 10:16:41 pm »
Well, a couple of years ago I decided to get involved in CPLD's, I chose Atmel's range over XILINIX.Atmel supply you with a language called cupl and XILINIX supply you with ABEL they are very similair.Now it turns out XILINIX have discontinued the xc9536 and the xc9572 chips and they are not 5V but 3.3V. So, fortunately I chose Atmel, as all their parts range are still available at Mouser.

The thing is though, CUPL is very buggy making it's usage time comsuming, but if like me you put up with it  and learn what you can do with it.Is there anybody here using cupl language? :popcorn:

Well, of course, CUPL was intended for PALs and GALs, where the devices were so simple that one could describe the functionality via simple combinational logic equations. Manual logic minimization via Karnaugh maps was very common. Very simple state machines could also be created. Like other posters said, if targeting CPLDs or FPGAs then I don't see any need to use CUPL. New tools are much more productive; Verilog supports low-level logic description via combinational statements but also higher-level behavioral language constructs, which gets more done in less time, no need to manually do logic minimizations because the tool does this automatically.

Important: CUPL also does not analyze timing automatically like modern tools. Concepts like Static Timing Analysis (STA) is vital to actually get any design working in an FPGA. Anything but the very simplest CPLD design should also use proper timing analysis.

Finally; I actually used CUPL about 10 years ago when I created the below dump-switch PCI card. Anything more complex than that project (i.e. CPLD) should use the CPLD vendor's modern toolset.

http://www.summitsoftconsulting.com/DumpSwitchCard.htm
Pocket-Sized USB 2.0 LS/FS/HS Protocol Analyzer Model 1480A with OTG decoding.
Pocket-sized PCI Express 1.1 Protocol Analyzer Model 2500A. 2.5 Gbps with x1, x2 and x4 lane widths.
https://www.internationaltestinstruments.com
 

Offline Bassman59

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #23 on: October 07, 2015, 10:43:48 pm »
Even for small (GAL18v10-sized) PALs?   I didn't know you could do that!
I don't know much about very simple devices. There is no technical reason why you can't use VHDL, but I don't know if manufacturers bothered to implement it.

For simple devices it will basically be instantiation of the available blocks and manual connections between them. I doubt you could use actual code.
"Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 Verilog as its Hardware Description Languages (HDL) for design entry. Then, it synthesizes and optimizes the entered design, and outputs a JEDEC or Intel® hex file for the desired PLD or CPLD (see Figure 1)."

It appears to synthesize GAL configurations from behavioral architectures. Cypress sold it in the '90s.

That "subset" of VHDL was limited to VHDL-87 syntax and it was very limited indeed, to the point of being unusable.
 

Offline Bassman59

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Re: ATMEL's CUPL language for their CPLD range of chips, what do you think.
« Reply #24 on: October 07, 2015, 10:47:30 pm »
How many of you are still using a third party synthesis tool?  What about third party simulation tools?

We use vendor-provided synthesis tools, so for Xilinx it's ISE (haven't done a Vivado design yet) and for Altera it's the Quartus II. Microsemi (Actel) provides a version of Synplify Pro which targets only their devices.

We have a VHDL-only license for Aldec Active-HDL. I'm doing something that targets an Altera device and its gigabit serializers, and the models are System Verilog, so I am using the ModelSim Altera for that.
 


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