MIPS Goes Open Source

[legacy]

OMG, it happened

Without question, 2018 was the year RISC-V genuinely began to build momentum among chip architects hungry for open-source instruction sets. That was then.

By 2019, RISC-V won’t be the only game in town.

Wave Computing (Campbell, Calif.) announced Monday (Dec. 17) that it is putting MIPS on open source, with MIPS Instruction Set Architecture (ISA) and MIPS’ latest core R6 available in the first quarter of 2019.

Art Swift, hired by Wave this month as president of its MIPS licensing business, described the move as critical to accelerate the adoption of MIPS in an ecosystem.

Going open source is “a big plan” that Wave CEO Derek Meyer, a MIPS veteran, has been quietly fostering since Wave acquired MIPS Technologies in June, explained Swift. Swift himself is a MIPS alumnus who worked at the company as a vice president of marketing and business development for four years.

Wave, which styles itself as a tech startup poised to bring “AI and deep learning from the datacenter to the edge,” sees MIPS as a key to advancing Wave’s AI into a host of uses and applications.

Included in MIPS instruction sets are extensions such as SIMD (single instruction, multiple data) and DSP. Swift promised that MIPS will bring to the open-source community “commercial-ready” instruction sets with “industrial-strength” architecture. “Chip designers will have opportunities to design their own cores based on proven and well tested instruction sets for any purposes,” said Swift.

Since 2000, 8.5 billion chips based on MIPS cores have been shipped, according to Swift. A broad range of customers are sticking with MIPS, including Microchip, Mobileye (now an Intel company), MediaTek, and Denso, Japan’s leading tier one.

Although commanding consistent respect among engineers, MIPS — whose ownership has been anything but stable — has struggled to build its ecosystem and generate momentum. MIPS trails far behind Arm today. Wave’s goal is to reverse a trend that looked for a long time like a downward spiral for MIPS.

Shrewd move
Asked how current MIPS partners reacted to Wave’s plan to open-source MIPS, Swift said, “Jaws dropped.” Among the comments: “Had this happened two or three years ago, RISC-V would have never been born.”

Asked if MIPS is coming to the open-source community too late, industry opinions appear split.

Linley Gwennap, principal analyst at the Linley Group, told EE Times, “MIPS is certainly behind RISC-V in mindshare in the open-source community.” He noted that MIPS was “unable to make this move sooner due to its various ownership transitions.”

Nonetheless, Gwennap added, “Given the advantages it [MIPS] offers, I think there is still time for it to gain design wins.”

Rupert Baines, CEO of UltraSoC, told EE Times, “Given RISC-V’s momentum, MIPS going open source is an interesting, shrewd move.”  He observed, “MIPS already has a host of quality tools and software environment. This is a smart way to amplify MIPS’ own advantage, without losing much.”

He said, for some SoC designers, “MIPS can be an alternative to adopting RISC-V.”

A U.K. company based in Cambridge, UltraSoC supplies advanced debugging and analytic technology for embedded systems and it is an active supporter of the RISC-V. However, Baines has always maintained that choosing a processor core “shouldn’t be a religious war.” For chip architects and designers tasked to deliver heterogeneous systems which include different processors, the ISA is only a small consideration, he said. A much bigger issue is coping with the problem of complexity in a “whole system.”

Industry observers agree on the maturity of MIPS.

Gwennap said, “The MIPS ISA is more complete than RISC-V. For example, it includes DSP and SIMD extensions, which are still in committee for RISC-V.”

In addition, MIPS is a commercially proven ISA that has already shipped billions over more than two decades, said Gwennap, “The MIPS software development tools are more mature.” Further, he noted, “MIPS also provides patent protection and a central authority to avoid ISA fragmentation, both of which RISC-V lacks. These factors give MIPS an advantage for commercial implementations, particularly for customer-facing cores.”

[legacy]

Wonder if this might result in a renewed interest in MIPS in general?

[SiliconWizard]

Great news!

I was wary of the MIPS buyout and am glad they took this decision which will help prevent MIPS from dying. As I said earlier, Wave Computing certainly didn't look like it had the shoulders to give MIPS a sustainable future on its own.

 

[ataradov]

Nope. There is really no point with RISC-V out there. It may prolong the death somewhat, but I doubt MIPS is ever coming back strong.

[NorthGuy]

I think they did it because there was no real way of profiting from MIPS. The only path is to oblivion.

I don't know about other vendors, but since Microchip bought Atmel, they moved their focus to SAM. I don't know if they are coming along with this, but they even wanted to rename SAMs into PIC32C, and even SAMs used in their new programming tools are marked as PIC32C. This doesn't look like Microchip is sticking with MIPS as the article seems to imply.

[brucehoult]

Great news! A bit of open-source competition will be good for everyone.

I really like the new nanoMIPS ISA (or at least encoding, with 16, 32, and 48 bit instructions, including instructions with embedded 32 bit literals) they introduced in the I7200 in May:

https://www.anandtech.com/show/12699/mips-announces-i7200-32bit-cpu-with-new-nanomips-isa

However I hear the MIPS compiler team was laid off before they could upstream any binutils or gcc support for nanoMIPS. They apparently sent a message to the mailing list saying they had patches ... and then they were gone.

They also laid off a half dozen (?) person debug tools team who I happen to know are now working on RISC-V stuff.

I just hope they haven't left this a year or three too late.

[brucehoult]

Looking at the announcement, it's including "the open source version" of MIPS r6 (whatever that means!) and microMIPS, but not nanoMIPS.

MIPS r6 is a very nice improvement over earlier MIPS versions, providing branches without delay slot, branch on comparison of two registers (like RISC-V) and some other good stuff. MicroMIPS is pretty meh though and doesn't have anywhere near as good code density as Thumb2 or RISC-V, let alone what nanoMIPS is claimed to provide.

[legacy]

I happen to know a couple of guys inside the old MIPS company when they were in business. I got a printed copy of the R10K (mips-4) user manual, but I am still looking for R12K, R14K and R16K (mips-5).

R10, R12, and R14K were used in the SGI IP30 workstation, which on DTB we are still supporting for Linux (and recently for XINU, but it's extremely experimental).

Hope someone will release these UMs!

[NorthGuy]

MIPS r6 is a very nice improvement over earlier MIPS versions, providing branches without delay slot, branch on comparison of two registers (like RISC-V) and some other good stuff.

The branch on comparison (such as BEQ) was in the MIPS from the beginning (or close to the beginning). It would be hard to get by without it when there's no flags. Even their unconditional branch is built as "BEQ zero,zero,target".

[David Hess]

Are they going to sue people which implement their ISA over patent infringement again?

Open source does not mean free of intellectual property encumbrance.

[andersm]

Patent issues are covered in the EETimes article.

[andersm]

MicroMIPS is pretty meh though and doesn't have anywhere near as good code density as Thumb2 or RISC-V, let alone what nanoMIPS is claimed to provide.

In my own code size tests I did some years ago, microMIPS generally produced smaller code than Thumb-2. I used the SQLite3 amalgamated source, since it's a single, large, self-contained source file that was simple to build. The test wasn't very scientific, and the output size difference varied rather wildly with optimization level, but apart from -O0 the result was in favour of microMIPS. I didn't spend the time analyzing where the difference came from, but I would say they are at least comparable.

[brucehoult]

MIPS r6 is a very nice improvement over earlier MIPS versions, providing branches without delay slot, branch on comparison of two registers (like RISC-V) and some other good stuff.

The branch on comparison (such as BEQ) was in the MIPS from the beginning (or close to the beginning). It would be hard to get by without it when there's no flags. Even their unconditional branch is built as "BEQ zero,zero,target".

I mean ordered comparison.

You can get by without condition codes if you have even as much as "Set Register to a LT b" and "Branch if register is zero" (or nonzero). Which is exactly what you did on MIPS until recently.

[legacy]

Are they going to sue people which implement their ISA over patent infringement again?

it happened in 2004, it should be passed 

[NorthGuy]

I mean ordered comparison.

What is "ordered comparison"?

[brucehoult]

I mean ordered comparison.

What is "ordered comparison"?

It is when you compare two registers and are interested in numeric ordering, not equality.

[NorthGuy]

It is when you compare two registers and are interested in numeric ordering, not equality.

I see. They didn't have this in older MIPS. Nice addition. It's always nice when you can do something with one instruction which required two instructions before.

I'm afraid it may be too late for improvements

[brucehoult]

It is when you compare two registers and are interested in numeric ordering, not equality.

I see. They didn't have this in older MIPS. Nice addition. It's always nice when you can do something with one instruction which required two instructions before.

I'm afraid it may be too late for improvements

They added branch on ordered comparison of two registers (with no delay slot!) in MIPS r6 in 2014.

As I said in the original message.

[legacy]

can you give an example of these "ordered comparisons"?

[legacy]

Saint Google says it's for FloatingPoint "An ordered comparison checks if neither operand is NaN. Conversely, an unordered comparison checks if either operand is a NaN".

NaN => Not a Number => FloatingPoint stuff 

[legacy]

LOL, digging into gcc error messages (-Werror=extra), I find this
"error: ordered comparison of pointer with integer zero"

[legacy]

• Ordered means that neither operand is a NaN.
• Unordered means that either operand may be a NaN.

In brief, fcmp&predicates does this:

• Ordered comparison expects both operands to be numbers.
• Unordered comparison returns true if one of the operands is NaN.

I am working with FixedPoint numbers, I have never used/implemented anything similar.

[NorthGuy]

• Ordered comparison expects both operands to be numbers.
• Unordered comparison returns true if one of the operands is NaN.

I've got confused the same way. "ordered" and "unordered" are standard terms for floats. But MIPS branches work with integers. What Bruce meant are comparisons other than equality/inequality, such as (a > b) or (a < b), as opposed to (a == b) or (a != b).

[legacy]

Code: [Select]

* Equality
 * [==]  teq  equal
 * [!=]  tne  not equal
 *
 * Relational
 * [<=]  tle  less equal
 * [< ]  tlt  less than
 * [>=]  tge  greater equal
 * [> ]  tgt  greater than


[donotdespisethesnake]

Sounds like it's not actually Open Source, just royalty free :

Wave said under its MIPS Open Initiative, participants – who will be required to register – will have access to the 32-bit and 64-bit MIPS ISA at no charge, without any licensing or royalty fees.

No doubt there will be an upsell to commercial paid-for proprietary stuff, e.g. for Waves special AI extensions etc.