Sum Ergo Demonstro RP2350 demo by lft

[ledtester]

About a month ago demo creator lft presented his "Sum Ergo Demonstro" video+audio demo for the RP2350:

Sum Ergo Demonstro -- lftkyro
https://youtu.be/v8zKDotYh9A

In this video he does a deep dive into how it was all implemented using the various capabilities of the RP2350 including the HST, PIO, interpolators and all the timing considerations that had to be taken into account. I found it to be a very fascinating technical presentation.

Microcontroller Magic: Under the Hood of “Sum Ergo Demonstro” -- lftkryo
https://youtu.be/0_9YS2tsdYc

[HwAoRrDk]

He talks about how on the Hazard3 RISC-V implementation, using an instruction that accesses a register immediately following an instruction storing to that same register imposes a 1-cycle delay (the example given is lw a0, DBG_PADOUT(a2) followed by lw a1, (a0)). Is this something specific to the Hazard3, or is it a quirk more widely shared by other RISC-V CPUs?

[aeg]

He talks about how on the Hazard3 RISC-V implementation, using an instruction that accesses a register immediately following an instruction storing to that same register imposes a 1-cycle delay (the example given is lw a0, DBG_PADOUT(a2) followed by lw a1, (a0)). Is this something specific to the Hazard3, or is it a quirk more widely shared by other RISC-V CPUs?

This is a pipeline stall due to a data hazard. It is inherent in all pipelined processor designs, not just RISC-V, when an instruction reading a register overlaps with a pipelined instruction writing the same register. Some processors have register renaming, which mitigates this (especially for small register sets) when the same register is used sequentially for different operations, but the pipeline stall is still unavoidable when one instruction depends on the register value loaded by a previous instruction. Compilers will try to schedule instructions so that instruction cycles that would otherwise be lost to pipeline stalls will instead be utilized for operations involving other registers.