Beginner problems with MachXO2

[ion]

I've been wanting to learn how to use FPGAs so I recently got a MachXO2 breakout board.  I read up a bit on VHDL and decided to make an 8 bit counter to drive the LEDs on the board.

The code runs fine in the simulator and gives the expected results, but once I got it to synthesize and uploaded the code to the board it didn't work.  All the LEDs stay lit, but I suspected they were just running at a very high frequency so I took some readings.

The LEDs were switching between 1.1MHz and 1.8MHz but not in any order - most around 1.5MHz.  I also mapped the CLK port to one of the pins and it read ~1.7MHz (should be ~ 3 Hz).  I'm not confident that these numbers are accurate other than they are far higher than they should be.

It is quite possible I might have missed a step somewhere - although I think I've got the hang of the Diamond IDE.
Or maybe I messed up the VHDL in a way that won't show up in the simulation?

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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

library machxo2;
use machxo2.all;

entity COUNT is
port( CLK : inout bit;
        CNT : buffer std_logic_vector (7 downto 0) := "00000000");
end COUNT;

library IEEE;
use IEEE.std_logic_1164.all;

entity Clk_gen is
port(CLKsig : inout bit);
end;


architecture Clk_behv of Clk_gen is

signal tick : std_logic;

component OSCH is
generic( nom_freq: string);
port( STDBY : in std_logic;
                OSC : out std_logic);
end component;

begin

Inst0: OSCH generic map (nom_freq => "3.02")
   port map ('0', tick);

process(tick)
variable counter: integer Range 0 to 500000;
begin
if (tick = '1') then
if (counter< 500000) then
counter := counter + 1;
else
counter := 0;
CLKsig <= not CLKsig;
end if;
end if;
end process;

end Clk_behv;


architecture Count_behv of COUNT is

component Clk_gen is
port( CLKsig : inout bit);
end component;

begin

inst1:Clk_gen port map (CLK);

process(CLK)
begin
if(CLK = '1') then

if (CNT = "11111111") then
CNT <= (others => '0');
else
CNT <= CNT + "1";
end if;

end if;
end process;

end Count_behv;

THe vector CNT drives the LEDs.  Any help is appreciated.

[vvanders]

What's the on-chip osc set to? It can be pretty wide range, 2Mhz to 133Mhz from a quick peek at the docs.

[ion]

I set it to 3.02 MHz, or at least that's what I think this line is doing:

Code: [Select]

      Inst0: OSCH generic map (nom_freq => "3.02")


[c4757p]

Code: [Select]

if (tick = '1')
if(CLK = '1')

These should really be

Code: [Select]

if (rising_edge (tick))
if (rising_edge (CLK))

Not sure what the exact behavior of the first will be, but I suspect not pretty. You're mapping your connections whenever tick and CLK are high, not just at the edge - that's non-sequential.

Can you get the software to render a schematic of the logic it generated?

[mikeselectricstuff]

without the "if rising-edge" it's just a priority encoder, so nothing will be latched.

 

[ion]

Code: [Select]

if (tick = '1')
if(CLK = '1')


But these are in

Code: [Select]

process(tick)
and

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process(CLK)

If I understood correctly the process only executes when the corresponding trigger has changed value.  If the value changed and is now a '1' then it must have been a rising edge right?
That said, the rising_edge() function seems better for triggering off clocks, thanks for pointing it out.

Can you get the software to render a schematic of the logic it generated?

Yes, I've attached the schematics below.  Actually, could someone let me know what the logic symbol for un4_tick represents?

[ion]

without the "if rising-edge" it's just a priority encoder, so nothing will be latched.

Ok, I'll see if changing the code fixes it.

[Bassman59]

Code: [Select]

if (tick = '1')
if(CLK = '1')

These should really be

Code: [Select]

if (rising_edge (tick))
if (rising_edge (CLK))


No, actually it should be:

Code: [Select]

foo : process (clk) is
begin
    if rising_edge(clk) then
        if (tick = '1') then
       end if;
    end if;
end process foo;
Assuming that the signal tick is a one-clock-wide strobe. If not, then you need to delay it and look for an edge in the usual way:

Code: [Select]

bar : process (clk) is
begin
    if rising_edge(clk) then
        tick_d <= tick;        -- delay flop for edge detect
        if tick = '1' and tick_d = '0' then -- on rising edge of tick
            .. do something ...
        end if;
    end if;
end process bar;
The point is that the rising_edge() function is used only on the clock signal. If you want to find the edge of a non-clock signal, you have to delay it and do the comparison.

[ion]

Thanks guys, using the rising_edge() function got it working (sort of - didn't realise the FPGA was hooked up to the LED's cathodes, but that was an easy fix).

Code: [Select]

if (tick = '1')
if(CLK = '1')

These should really be

Code: [Select]

if (rising_edge (tick))
if (rising_edge (CLK))


No, actually it should be:

Code: [Select]

foo : process (clk) is
begin
    if rising_edge(clk) then
        if (tick = '1') then
       end if;
    end if;
end process foo;

Actually tick and clk are used is separate processes, not even in the same module.  So replacing the = '1' with rising_edge() in each case was enough to make it work.
Tick and clk are both clock signals - 3 MHz and 3 Hz respectively.

The point is that the rising_edge() function is used only on the clock signal. If you want to find the edge of a non-clock signal, you have to delay it and do the comparison.

Good to know, thanks.