Author Topic: 32F4 - is there a spec on the 50MHz clock from the ETH PHY?  (Read 3251 times)

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Online nctnico

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Re: 32F4 - is there a spec on the 50MHz clock from the ETH PHY?
« Reply #25 on: October 07, 2022, 07:45:10 am »
Likely the pll inside the STM32 is based on an adjustable digital delay line with fixed intervals instead of a VCO. Such digital PLLs alway produce huge amounts of jitter ( up to 100s of ps)
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline wek

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Re: 32F4 - is there a spec on the 50MHz clock from the ETH PHY?
« Reply #26 on: October 07, 2022, 08:32:30 am »
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It's just that apparently the PLL in the STM32F4 itself is crappy.


Sure, all analog features on STM32 are crappy when compared to ideals. But as this is not just an arduino chitchat, can we appreciate how well they work being mixed with raging digital, and how good value for the eurocent they are?

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I'm sure the LAN8742's PLL has proper characteristics.

Building a single-frequency PLL is "easy".

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The above is the circuit I am using. It is also what ST use on their dev board.

Not on the EVAL... oh, quite a ride that one was...

JW

 

Offline peter-hTopic starter

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Re: 32F4 - is there a spec on the 50MHz clock from the ETH PHY?
« Reply #27 on: October 07, 2022, 08:52:38 am »
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Likely the pll inside the STM32 is based on an adjustable digital delay line

That makes much more sense, given that 50MHz is all that's ever needed.

Good to know I am not doing it wrong :) I have ~15 boards now working solidly.

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all analog features on STM32 are crappy when compared to ideals

Do you mean anything specifically? Sure, all ADCs and DACs on CPUs are "crap". I've never seen one on which the last couple of bits weren't noise.

From the ST forum post:

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- soldering the SMD 50MHz oscillator is quite impossible, given the cramped space (I don't quite understand why ST spared down a $1 part from a $350 board). I solved it through using a much smaller oscillator (2mm x 3mm ASE series of Abracon, instead of the ''original'' 5mm x 7mm), having ''extended'' its contacts to the PCB pads using short wires
- while the oscillator is located quite close to the PHY, the 50MHz clock (possibly the fastest signal on the board) is then routed through some 10 cm to the extension header, and back further 5 cm to the mcu. The performance was then, ehm, marginal (it sort of worked when loaded by a LA's probe). Had to cut the track to the extension header and reroute it the shortest possible way by a wire, which given the track width was quite a challenge too

I don't mean to sound like a smart arse :) but I would never use a 50MHz oscillator because of the EMC issue. And yes the ST dev kit runs signals for miles around the place. They are CE (EMC) exempt so they can do it.

I also don't like Abracon as a company. If I am going to pay top dollar I make sure I get a premium part e.g. Kyocera, AVX, etc.

« Last Edit: October 07, 2022, 09:04:19 am by peter-h »
Z80 Z180 Z280 Z8 S8 8031 8051 H8/300 H8/500 80x86 90S1200 32F417
 

Online nctnico

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Re: 32F4 - is there a spec on the 50MHz clock from the ETH PHY?
« Reply #28 on: October 07, 2022, 09:59:36 am »
NXP's LPC series has good ADCs. I even had trouble to make these more noisy to get a few more bits out of them.

About the clock: on a 4 layer board with a solid ground plane it is almost impossible to screw up a layout where it comes to EMC compliance.
« Last Edit: October 07, 2022, 10:01:41 am by nctnico »
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 


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