I just proposed the good and cheap way to get low jitter ADC measurements.
It allows to decrease ADC phase noise and get higher speed stream from ADC with less CPU load.
And it provide you much less ADC phase noise and more easy solution than using internal ADC with DMA.
There are possible other solutions but they are not so simple and cheap, because it requires more expensive components, such as FPGA. Which are more complicated and will be overkill for the topic starter needs.
While internal ADC phase noise is limited with internal timers jitter, which is not good and you will get higher phase noise. With high clock jitter, you will get more noisy ADC output.
Since topic starter needs ADC with about 5 kHz sample rate, using audio codec will be a nice solution. Because it already has all things to capture ADC data with low clock jitter and with high dynamic range and stream that data to CPU with sample rate up to 384 kHz.
By using external audio codec, you can clock it from ultra low phase noise clock source and get ready to use sample stream... without having to worry about samples being taken with configured sample rate and with minimum clock jitter.
The topic starter asked for the best way to trigger ADC. And trigger it from dedicated ultra low phase noise clock source is the best way to get maximum ADC performance and minimize phase and amplitude noise on ADC output.
Any clock source from microcontroller is not good for ADC due to a very high clock jitter. Just open microcontroller datasheet and check it's jitter on GPIO, it is very high. FPGA has better jitter performance than microcontrollers, but still very bad for ADC clock. This is why using dedicated ultra low phase noise clock source is the best way to trigger ADC in order to get the best ADC performance.