Bugs running MCS BASIC-52 on 8052

[free_electron]

you have not seen what this thing can do until you instantiate the oregano designs 8051 core, a ram and a rom in an Altera FPGa and clock it at 400 MHz ....
That is one speedy basic machine !

[JohnnyQuest1111]

All that crazy speed for MCS-BASIC and the slowest link is the serial port ... if the program prints output ... or the human operator ... if the program is *WAITING* for user input. 

I can appreciate the fun of the project.

At 400MHz, what applications could this blazing fast MCS-BASIC support?

Peace and blessings,
JQ

[0db]

Altera FPGa and clock it at 400 MHz ....

400Mhz? on which fpga?

[brucehoult]

This thread is very interesting. A few days ago I ordered a handful of 65C02 chips (and 65C22 VIA), some 32Kx8 SRAMs, some 32Kx8 EEPROMs (and a programmer) and a bunch of latches, inverters, 2 input NAND and NOR gates, 8 input NAND gates. Planning to play around with all this stuff on a breadboard.

No reason not to play with the same stuff with 8051 or other old CPUs also. I already had plans to try the SRAM on the ATMega2560 eternal bus (the 8 bit latch chip is needed for this, to demultiplex the data bus and LSBs of the address)

A cool thing about the 65C02 is it's fully static, so can be run at 0 Hz and stopped or single stepped by hand. Does that apply to 8051 also? I think the Microchip ones are? And also Z180 but not Z80?

[retrolefty]

And also Z180 but not Z80?

 Z-80 was always fully static and also had support for auto refresh of the DRAM of the day.

[brucehoult]

And also Z180 but not Z80?

 Z-80 was always fully static and also had support for auto refresh of the DRAM of the day.

I don't believe the NMOS ones were.

[free_electron]

All that crazy speed for MCS-BASIC and the slowest link is the serial port ... if the program prints output ... or the human operator ... if the program is *WAITING* for user input. 

I can appreciate the fun of the project.

At 400MHz, what applications could this blazing fast MCS-BASIC support?

Peace and blessings,
JQ

i stripped the uart and converted that into a ftdi245 port. it was speedy ...
The oregano core is one of those 'turbo' cores. Most instructions process in a single clocktick. It is free. You can get the verilog. I ran it on a Cyclone 5 i believe. PLL was set to 420MHz. it's been a while. i mapped the ram and rom in the FPGA so nothing external was needed. the rest were simply GPIO pins.

[JohnnyQuest1111]

i stripped the uart and converted that into a ftdi245 port. it was speedy ...
The oregano core is one of those 'turbo' cores. Most instructions process in a single clocktick. It is free. You can get the verilog. I ran it on a Cyclone 5 i believe. PLL was set to 420MHz. it's been a while. i mapped the ram and rom in the FPGA so nothing external was needed. the rest were simply GPIO pins.

Beautiful!

I used to be an FAE for XILINX. Was taught all about the parts and how they work, tools and all. But I never had the time to do anything like that on my own.

Peace and blessings,
JQ