Author Topic: Bus Arbitration Process I2C  (Read 933 times)

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Offline Mtech1Topic starter

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Bus Arbitration Process I2C
« on: October 03, 2023, 02:04:43 pm »
I'm trying to understand how a single master takes control of the I2C bus when multiple masters attempt to communicate simultaneously. I've reviewed the I2C user manual, particularly Chapter 3.1.8 on arbitration in UM10204. It mentions that arbitration functions with a WIRED-AND operation. In logical AND terms, if both input signals are '1,' the output becomes '1.' . if either or both input signals are '0,' it results in an output of '0.'

I've come across a table like this:

M1 | M2 | Output
0   | 0   | 0
0   | 1   | 0
1   | 0   | 0
1   | 1   | 1

Please help to understand how does one master device take control of the I2C bus when multiple masters are attempting to communicate concurrently with arbitration process when output is open collector?
 

Offline Marco

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Re: Bus Arbitration Process I2C
« Reply #1 on: October 03, 2023, 02:49:32 pm »
The master which tries to signal high (ie. does not pull low) but finds the bus low (ie. another master is pulling low) gives up. If they both try the send the exact same message at the same time, well then it didn't matter :)

This is possible because the bus is open drain and clocked.
« Last Edit: October 03, 2023, 02:51:33 pm by Marco »
 

Offline wek

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Re: Bus Arbitration Process I2C
« Reply #2 on: October 03, 2023, 02:52:50 pm »
The two masters either try to talk to the same slave and want to tell the same (e.g. write the same data into the same address, or read from the same address) - and in that case the two SDA sequences are identical and there's no conflict, no one of the masters need to take over - or there is at least one bit difference.

In the latter case, one of the masters (say M1) outputs onto SDA 0 and the other (say M2) 1. Due to wire-OR and open collectors, SDA is in state 0. Each master reads back after each bit the state of SDA, and as M2 intended to output 1 but the SDA is at 0, this master simply gaves up, and the rest of the stream is under control of the other master i.e. M1.

JW
 

Offline Mtech1Topic starter

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Re: Bus Arbitration Process I2C
« Reply #3 on: October 03, 2023, 10:20:27 pm »
I'm still unclear  of the arbitration process in I2C communication. From my understanding, the I2C bus is ideally in a high state because of its pull-up resistors.  both the outputs of two masters are connected to the inputs of a wired AND function. What happens when two attempts to drive sda low at time. How one know that I2C bus is busy because some other master has take control on the bus.
 

Online DavidAlfa

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Re: Bus Arbitration Process I2C
« Reply #4 on: October 03, 2023, 11:11:54 pm »
Because the i2c hardware monitors SCL/SDA lines just before sending the start condition.
Finding any of them low, it will generate a bus busy error, needing handling in software.
It's really hard that multiple masters access the i2c bus in the exact same moment within, let's say, 10ns, so only the fastest one will keep going.
The software can then generate different delays before retrying based on the mcu unique ID or serial number, one might retry in 50us and the other in 60us.
« Last Edit: October 03, 2023, 11:15:09 pm by DavidAlfa »
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Online PCB.Wiz

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Re: Bus Arbitration Process I2C
« Reply #5 on: October 04, 2023, 03:04:59 am »
I'm still unclear  of the arbitration process in I2C communication. From my understanding, the I2C bus is ideally in a high state because of its pull-up resistors.  both the outputs of two masters are connected to the inputs of a wired AND function. What happens when two attempts to drive sda low at time. How one know that I2C bus is busy because some other master has take control on the bus.

The masters have to read back the lines, to check against what they wrote.
If they sense a differences (someone else is driving low, when they expected high) then they release the bus.
The winning master, has no idea the other master was present.

In theory, two masters could address the same peripheral, with the exact same address and data, and never have a contention fail, even tho both were driving the bus.
 

Offline Mtech1Topic starter

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Re: Bus Arbitration Process I2C
« Reply #6 on: October 04, 2023, 03:11:43 am »
It seems that when two masters attempt to take control of the I2C bus, the one that first pulls the SDA line low while the SCL is high gains control. How does one master succeed in asserting control by pulling SDA low before the start condition?
 

Online PCB.Wiz

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Re: Bus Arbitration Process I2C
« Reply #7 on: October 04, 2023, 03:38:16 am »
It seems that when two masters attempt to take control of the I2C bus, the one that first pulls the SDA line low while the SCL is high gains control.
How does one master succeed in asserting control by pulling SDA low before the start condition?

The SDA =\_ is the start condition, thus if any master sees SDA go low 'before expected' when SCL is high, they know another master has just issued a START.
 

Offline Mtech1Topic starter

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Re: Bus Arbitration Process I2C
« Reply #8 on: October 04, 2023, 12:49:49 pm »
My current confusion is in understanding how both masters monitor the SDA line before generating the start condition. What's role of AND wired operation in arbitration process
 

Offline ejeffrey

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Re: Bus Arbitration Process I2C
« Reply #9 on: October 04, 2023, 01:58:57 pm »
The wired and is a fundamental part of the i2C protocol, it lets devices drive the "low" state without risk of conflict with another device driving a "high" and generating an indeterminate logic level.  It's used not only for multi master arbitration but for regular master / slave communication.
 

Offline Marco

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Re: Bus Arbitration Process I2C
« Reply #10 on: October 04, 2023, 01:59:09 pm »
I'm still unclear  of the arbitration process in I2C communication. From my understanding, the I2C bus is ideally in a high state because of its pull-up resistors.  both the outputs of two masters are connected to the inputs of a wired AND function. What happens when two attempts to drive sda low at time. How one know that I2C bus is busy because some other master has take control on the bus.
It doesn't matter, since there is no corruption. There can only be corruption if a master tries to signal low after it detected another master pulling low when it signalled high, which doesn't happen because the master which tried to signal high immediately stops signalling altogether.

The first high when the other is low, looses access for that message.

PS. stop thinking in logic terms, you're confusing yourself. Think only about high and low and forget about AND for a moment. Yes it's a diode logic AND, but that's really besides the point.
« Last Edit: October 04, 2023, 02:27:52 pm by Marco »
 


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