Electronics > Microcontrollers

Bus Arbitration Process I2C

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I'm trying to understand how a single master takes control of the I2C bus when multiple masters attempt to communicate simultaneously. I've reviewed the I2C user manual, particularly Chapter 3.1.8 on arbitration in UM10204. It mentions that arbitration functions with a WIRED-AND operation. In logical AND terms, if both input signals are '1,' the output becomes '1.' . if either or both input signals are '0,' it results in an output of '0.'

I've come across a table like this:

M1 | M2 | Output
0   | 0   | 0
0   | 1   | 0
1   | 0   | 0
1   | 1   | 1

Please help to understand how does one master device take control of the I2C bus when multiple masters are attempting to communicate concurrently with arbitration process when output is open collector?

The master which tries to signal high (ie. does not pull low) but finds the bus low (ie. another master is pulling low) gives up. If they both try the send the exact same message at the same time, well then it didn't matter :)

This is possible because the bus is open drain and clocked.

The two masters either try to talk to the same slave and want to tell the same (e.g. write the same data into the same address, or read from the same address) - and in that case the two SDA sequences are identical and there's no conflict, no one of the masters need to take over - or there is at least one bit difference.

In the latter case, one of the masters (say M1) outputs onto SDA 0 and the other (say M2) 1. Due to wire-OR and open collectors, SDA is in state 0. Each master reads back after each bit the state of SDA, and as M2 intended to output 1 but the SDA is at 0, this master simply gaves up, and the rest of the stream is under control of the other master i.e. M1.


I'm still unclear  of the arbitration process in I2C communication. From my understanding, the I2C bus is ideally in a high state because of its pull-up resistors.  both the outputs of two masters are connected to the inputs of a wired AND function. What happens when two attempts to drive sda low at time. How one know that I2C bus is busy because some other master has take control on the bus.

Because the i2c hardware monitors SCL/SDA lines just before sending the start condition.
Finding any of them low, it will generate a bus busy error, needing handling in software.
It's really hard that multiple masters access the i2c bus in the exact same moment within, let's say, 10ns, so only the fastest one will keep going.
The software can then generate different delays before retrying based on the mcu unique ID or serial number, one might retry in 50us and the other in 60us.


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