Electronics > Microcontrollers

ch32v307, risc-v minicore with ethernet

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newbrain:

--- Quote from: newbrain on May 21, 2022, 04:18:48 pm ---
--- Quote from: SiliconWizard on May 16, 2022, 04:13:12 pm ---I suspect there may be other things done using this attribute, depending on the content of the ISR.
--- End quote ---
You are quite certainly right, I'll check the generated assembly in the two cases (and study RISC-V exception and interrupt model).

--- End quote ---
In fact, using __attribute__((interrupt("WCH-Interrupt-fast"))) is equivalent to __attribute__((naked)), plus asm volatile("mret") to return from the ISR.
The naked avoids that all the registers are stacked at entry (and popped at exit), and the mret will provide the return to user mode from machine mode.

At least, that worked with some simple test code...

woofy:

--- Quote from: woofy on May 14, 2022, 03:43:05 pm ---Does anyone know if the API documentation for the TCP/IP stack is available anywhere?

--- End quote ---

I asked on github, it's coming!
https://github.com/openwch/ch32v307/issues/20

martinribelotta:
Ok, with my ch32v307 board in hands, I have started coding a more confortable software environment than the MRS eclipse+modified gcc, and this is the (work in progress) result:

https://gitlab.com/eta-for-ci/ch32v307-gnumake

This provides the latest pheriperal library and the last rt-thread (4.0.4, not the oldest 3.x bundled with the example project)

By now, only gpio and usart driver is working (plus finsh shell) but in the sucessive days I will push more updates (specially adc/dac/pwm drivers plus usb dev driver)

The gcc required is risc-v embed (from xpack) but the oldest (8.x) gcc bundled with MRS toolchain work fine (my code do not use WCH-Interrupt-fast extension, but the CI is build around it for compatibillity)

The only MRS toolchain that this require now is the openocd with the MRS modifications (I was fail epically in compile it from the sources previously posted here)

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