Can you give me VHDL test bench for (I called my first project test):
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity test is
port(
sw0 : in STD_LOGIC;
sw1 : in STD_LOGIC;
LED0 : out STD_LOGIC;
LED1 : out STD_LOGIC
);
end test;
architecture test of test is
begin
LED1 <= sw1;
LED0 <= sw0;
end test;
I need some periodic signal on sw0 and sw1.