EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: fourtytwo42 on May 06, 2018, 12:18:34 pm
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Hello everyone, I am having trouble figuring out how to configure any timer in the STM32F3xxxx to drive a half bridge SMPS. It seems it is able to produce "complimentary" outputs where one is the inverse of the other but that is not what I need.
What I am looking for is at say 25% duty cycle output A is on for 25% whilst B is off, then B is on for 25% whilst A is off.
Am I going blind, I have read the REF manual again and again and tried AN4776 (timer cookbook) all to no avail.
Has anybody out there done this before and be willing to give me a clue/s please :)
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Isn't what you need complementary outputs with programmable dead-time?
The advanced timer TIM1 can be used as "complementary PWM outputs with programmable inserted dead-times".
The datasheets themselves only describe functionalities, but to get more details, download the reference manual and look for "Complementary outputs and dead-time insertion".
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Ninjaed by a wizard...
I'll just provide the link to the ref manual (http://www.st.com/content/ccc/resource/technical/document/reference_manual/4a/19/6e/18/9d/92/43/32/DM00043574.pdf/files/DM00043574.pdf/jcr:content/translations/en.DM00043574.pdf), and the relevant chapters: 20.3.15, and 20.4.18.
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Thank you for your replies :) As I said I have already read the referance manual from cover to cover BUT
Complimentary mode with deadtime doesnt do it as that only covers the case of 100% duty cycle with deadtime.
Yes it could drive something like a CCFL inverter where the duty cycle is always near 100% but not a variable power smps where the duty cycle may vary from maybe 1-99%. Another way to consider a half-bridge is the two drive signals need to look like a push-pull circuit using a centre tapped transformer and two switches that are on on alternate pwm cycles for a variable (but importantly identical) duty cycle.
Unfortunatly the complimentary mode takes the singular OCyREF internal pwm output and applies it to the true and compliment outputs with deadtime insertion but otherwise simeltaniously, not alternatly.
I hope I am making sense.
I am seriously worried this thing cannot hack it and if thats the case I would be suitably astonished, so I am hoping I have just missed something somewhere |O
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You might be looking for this, then:
20.3.13 Combined PWM mode
Combined PWM mode allows two edge or center-aligned PWM signals to be generated with programmable delay and phase shift between respective pulses.
I've never used this mode so I cannot provide much guidance...
But is it something like this what you're trying to achieve?
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I did look at that, in particular figure 177 but sadly all the output signals are identical in the two pwm cycles shown, i.e. there is nothing alternate about them.
Yes I am trying to acheive the signals in your very good diagram but the critical factor is they must be the same width derived from a single duty cycle register.
The way ST are generating a pattern like that is to use two seperate channel comparitors from the same master pwm and that simply won't work as there is no sane way to simeltaniosly adjust the duty cycle.
I cannot fathom why they just didnt put a flip-flop in the output logic like Microchip, I think I am going to have to put the STM32 in the graveyard after a lot of time invested and look for something else :(
P.S. Thank you very much for your help :)
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It's possible to have the CCRx registers loaded in the actual comparator register only at update events, rather than at write time.
Could this ease the synchronisation?
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs.
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I think it would were I not doing other things such as using an analogue comparitor input to determine the actual termination of the output pulse irrespective of the duty cycle setting so I am afraid that means it will only work if the pwm is post processed in a flip-flop manner rather than the way ST do it. Sadly my initial evaluation only consisted of checking there were at least two outputs per pwm and that analogue comparitors were able to terminate the pwm in an auto-restart next cycle manner. All those things it does but I did not expect the two outputs to be unable to operate in push-pull/half-bridge mode so I guess I got caught with my pants down :-[
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Ah, Ok...
Getting more and more complicated. Are you using the break function with input from the comparator?
Having never used an F3, and this timer functions, I don't think I can help you much ::)
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What's your target PWM frequency? If it's low enough, you could handle the IO's yourself in simple timer interrupts, without an excessive penalty.
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Yes I am/would be using the break function, but now ........
Yup the F3 had the right mix of analogue and digital for me, similar to the PIC24EVxxxMCxxx series that I was using.
Reason for change, bogged down in Errata/workarounds and undocumented bugs in the PIC PWM BUT at least driving a half bridge it can do with eyes shut hahaha
Anyway just so everybody knows, the STM32F3 cannot drive half-bridge or push-pull smps's!! Not much of a PWM :(
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What's your target PWM frequency? If it's low enough, you could handle the IO's yourself in simple timer interrupts, without an excessive penalty.
Only 25Khz (but a later target of 125Khz) but having experienced the instruction set and actual vs claimed execution rate I wouldn't like to try it and there is a lot of complexity beyond a simple PWM :) Big MOSFETS are expensive as is replaceing burnt pcb's :)
I think I am making excuses here, it might be worth thinking about but it would be hard to keep the interrupt latencies low enough as there are lots of other realtime control functions going on and thats where the MIPS were supposed to be used.
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Hi . My precious friend. I'm having the same problem. have you found a solution? Thank you. sorry for my english
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Hi, sorry for the late reply, no I never did find an acceptable solution so I dumped the entire chip and use PIC24EPxxxMC series for the job instead. The only other alternative would be to add a PLD external to the STM32.
I evaluated many ARM based microcontrollers and they all suffer the same problem so obviously the PWM IP comes from a common source (ARM).
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thank you .