FPGA IO

[electosleepy]

I want to drive an LED from an Artix 7 FPGA pin for debugging. The IO bank is 3.3V and the IO standard is LVCMOS33. There is a note that the says the following;

4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.

How is the drive strength determined? Is it determined by software or hardware?

[ataradov]

It is specified in the UCF file as NET <name> DRIVE = "<value>"; where value is a number in mA (one of the supported ones).

[electosleepy]

Thanks for the answer, is there any potential to cause damage to the IO pin? For example if I limit the current through the LED to 16mA with a resistor but the drive current was set lower accidentally to 4mA? Would the IO pin only output 4mA or would it try to draw more current and increase to 16mA?

[ataradov]

Drive strength is the limit. There will be no harm if the output is set high and completely shorted to ground externally. The current will be limited to the specified value.

I think all it does is enable a series resistor of varying value. So any external resistors will limit the current even further.

[hamster_nz]

Drive strength is the limit. There will be no harm if the output is set high and completely shorted to ground externally. The current will be limited to the specified value.

I think all it does is enable a series resistor of varying value. So any external resistors will limit the current even further.

Drive strength doesn't work that way. You still should use a current limiting resistor, as an FPGA pin can push 50mA into the LED. If you don't believe me, test it.

What drive strength does set as I understand it is this. When you are pulling or pushing X mA to/from the pin, the voltage at the pin will still be a valid high or low level for that I/O standard.

e.g. If the minimum logic high level for your I/O standard is 2.5V, with a drive strength of 12mA you can drive loads of around 200 Ohm to ground and still see 2.5v at the pin. If your load has lower resistance then 200 ohm, then you will get more than 12mA and your logic high level will drop below 2.5V.

[electosleepy]

So if I had a load that was 200 ohm with a drive strength of 4mA I would only see 0.8V on the pin (V=iR, 0.8V = 200R*0.004A) as it must be equal to equal to voltage dropped across the 200 ohm resistor to satisfy KVL. Whereas if the drive current was 12mA I would see 2.4V at the pin.

[tggzzz]

Drive strength is the limit. There will be no harm if the output is set high and completely shorted to ground externally. The current will be limited to the specified value.

No. Full stop.

You have to look at the I-V output curve for the specific IO type to determine what the short circuit (to ground or Vcc) current will be. The short circuit current will probably be high enough to damage the IC in one way or another.

[hamster_nz]

I'm a firm believer that a couple of measurements is more value than a thread full of general advice and supposition....

Test 1

FPGA :  Artix-7 35T - Basys3, high speed PMOD port (no series resistor)
IO Standard : LVCMOS33
Drive Strength :  12 mA (default)
Slew : Slow (default)
Pullup : None (default)

Constraints:

Code: [Select]

set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports jb1]


Results:

Open Circuit voltage 3.27 V
Through a 10 Ohm to ground 0.523 V.

I = V/R = 0.523/10 = 52 mA.

Power power dissipation in FPGA = approx 2.77 V at 52 mA =  144mW.

Test2

FPGA :  Artix-7 35T - Basys3, high speed PMOD port (no series resistor)
IO Standard : LVCMOS33 
Drive Strength :  4 mA
Slew : Slow (default)
Pullup : None (default)

Constraints:

Code: [Select]

set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports jb1]
set_property DRIVE 4 [get_ports jb1]

Results:

Open Circuit voltage: 3.28 V
Through a 10 Ohm to ground: 0.232 V.

I = V/R = 0.232/10 = 23 mA.

Power power dissipation in FPGA = approx 3.05 V at 23 mA =  70mW.

Conclusion
* Drive strengths aren't current limits. Anybody who says anything else is mistaken
* You should still put a resistor on an LED to correctly limit current.
* As a benefit it also moves significant heat out of the FPGA, (100mW per LED at high currents)
* My FPGA pin still works - so it is robust to shorts, at least for a few minutes. Don't be afraid to play

Anybody want to argue?

[tggzzz]

Conclusion
* Drive strengths aren't current limits. Anybody who says anything else is mistaken
* You should still put a resistor on an LED to correctly limit current.
* As a benefit it also moves significant heat out of the FPGA, (100mW per LED at high currents)
* My FPGA pin still works - so it is robust to shorts, at least for a few minutes. Don't be afraid to play

Anybody want to argue?

It is conceivable that overheating might permanently change an I/O parameter while leaving it still basically functional. Examples of such parameters could include speed and threshold shifts.

That doesn't change the recommendations, though.

[Siwastaja]

As explained above, drive strength is (probably) implemented by varying number of parallel MOSFETs.

When driving an LED, you are dissipating a certain amount of power anyway.

My opinion is that you should do it in external resistor as much as possible, to minimize power dissipation in the FPGA -- hence, use the largest drive strength setting.

Usually, when you calculate the resistor value for the LED, you ignore IO transistor Rds(on). When using the highest strength, the resistance in IO bank is smallest and the error in LED current calculation is smaller.

[electosleepy]

So how do I know what the maximum current rating for each pin is? I have tried looking for a maximum current rating in these documents and have not been able to find it?

http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

If the drive strength does not limit the current am I trying to limit the current to the drive strength?

[tggzzz]

So how do I know what the maximum current rating for each pin is? I have tried looking for a maximum current rating in these documents and have not been able to find it?

http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

If the drive strength does not limit the current am I trying to limit the current to the drive strength?

You must design the external circuit in such a way that the published specifications are not violated.

My design strategy would be to:

• define the current my external circuit needs, in this case the current through the LED
• choose the lowest drive strength that satisfies (1)
• knowing (2) you can look up the range of output voltages when driving that current
• insert an external resistor that will ensure that, given (3) and the range of LED forward voltage, the current through the LED is (1)

If you can't satisfy all those constraints simultaneously, you will need a more complex external circuit - probably involving a FET or BJT.

[mark03]

Conclusion
* Drive strengths aren't current limits. Anybody who says anything else is mistaken
* You should still put a resistor on an LED to correctly limit current.
* As a benefit it also moves significant heat out of the FPGA, (100mW per LED at high currents)
* My FPGA pin still works - so it is robust to shorts, at least for a few minutes. Don't be afraid to play

Anybody want to argue?

Sure, why not 

With a blue or green LED, LVCMOS33, and one of the lower drive levels, I think this is splitting hairs.  Sure, you could move a few mW of heat off-chip, but at least you're not going to damage anything.  From my [very] quick skim of the DC/switching characteristics, it looks like the drive-strength currents may be specified at nominal Voh minus 0.4V.  The load line is going to be just fine for an LED of comparable forward voltage.

Then again, if you want to be robust against accidental mis-configuration of the FPGA...

[rstofer]

So how do I know what the maximum current rating for each pin is? I have tried looking for a maximum current rating in these documents and have not been able to find it?

http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Datasheet Table 8 for LVCMOS33 points to Note 4 for Iol and Ioh which limits the drive current to those selected values.  Pick one...

It is doubtful (in my mind) if every single output pin could drive 12 mA without overheating the package.  Somehow, I didn't see a spec for TOTAL output current.  It's a common parameter for microcontrollers.

If I were driving an LED, I would calculate the resistor based on 3.3V to the series resistor and work it out for an LED current <= 12 mA.  Look at how the pros do it:
https://reference.digilentinc.com/_media/arty:arty_sch.pdf

For the standard LEDs, Digilent is using a 330 ohm resistor.  For the multi-color LEDs, they use a transistor driver.

I like to add 330 ohm resistors to all IO pins, input or output.  No matter how I misconfigure the board, I can't damage a pin by shorting beyond the resistor.  In this new world, I now have to specify 12 mA even though the resistor will limit the current to something less than that.


If the drive strength does not limit the current am I trying to limit the current to the drive strength?

[electosleepy]

I'm only guessing that they don't state a maximum current rating like microcontroller as the IO banks can have a range of voltages and there are a number of different IO standards. I'm guessing as I do not have an FPGA to test with, that if the current is less than or equal to the drive strength then it will be certain that you see Vcco across the GPIO pin and ground.

From my [very] quick skim of the DC/switching characteristics, it looks like the drive-strength currents may be specified at nominal Voh minus 0.4V

I think that Voh - 0.4V is just the threshold that you have to be within to achieve a logic high. As shown by the experiments done by hamster_nz, if more current is allowed to flow then you will subsequently see a much lower voltage across the GPIO pin.

[tggzzz]

I'm only guessing that they don't state a maximum current rating like microcontroller as the IO banks can have a range of voltages and there are a number of different IO standards. I'm guessing as I do not have an FPGA to test with, that if the current is less than or equal to the drive strength then it will be certain that you see Vcco across the GPIO pin and ground.

Xilinx give far more information on that for their IOs, because IO behaviour is critical to their high speed analogue behaviour. Make no mistake, the IO is analogue and has many analogue behavioural characteristics.

I presume other FPGA manufacturers do the same.

[electosleepy]

Some resources that I have found;

Raspberry Pi drive strength - https://www.scribd.com/doc/101830961/GPIO-Pads-Control2
Altera drive strength application note - https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an476.pdf

[Kilrah]

There will be a number of parallel MOSFETs driving one IO, and how many MOSFETs gets turned on determines max driving capability. You can set that in pin assignment window (at least for Altera and Lattice devices).
The current limitation is for the sake of EMI and SI control since the rise time of a modern FPGA is quite short, so the controlling of rise current became very important in unshielded or unterminated data lines.

Had a good example of that recently, I'm working on a device that uses an STM32 uC, has a high resolution color LCD and some audio output through speakers and a headphone jack. The speakers would have a slight buzz, while the headphones (for which the plug is on the same secondary board as the LCD, and thus the lines to it share the same flex cable) were very noisy, and it was obvious that audio noise depended on screen contents.

Don't know why but I somehow got the idea of trying to reduce the drive strength of the GPIO lines which were originally set pretty randomly for everything in the product, and actually at the fastest (ST labels them as frequencies of 2, 25, 50, 100MHz, probably for a given load capacitance that I didn't check) for the LCD. Reducing the drive strength while keeping an eye on the signals showed that 2MHz still gave perfectly good signal integrity and completely eliminated the noise in the audio.