Hi everyone,
I've hit a confusing situation while designing with the Allwinner H6 V200 SoC and DDR3L memory.
Based on the H6 V200 documentation (Rev 1.1):
The SDRAM controller supports "3 bank signal lines" (section 4.1.1)
https://linux-sunxi.org/images/4/46/Allwinner_H6_V200_User_Manual_V1.1.pdfThe DRAMC "automatically handles memory management, initialization, and refresh operations" and "hides details of the required address, page, and burst handling procedures"
The memory controller works in "half rate mode" to simplify chip system integration
However, looking at the actual signals:
H6 shows SBA[1:0] for Bank Address
H6 shows SBG[1:0] for Bank Group Address (which seems to be a DDR4-related)
https://linux-sunxi.org/images/5/5c/Allwinner_H6_V200_Datasheet_V1.1.pdf - page 44
Interestingly, every open source project I found for H6 uses LPDDR3 instead, where bank address lines are either grounded or left unconnected.
I'm planning to use a 2Gb DDR3L F-die SDRAM with:
x16 I/O configuration
Speed bins from DDR3-800 to DDR3-1866
1.35V operation
8 banks requiring BA0-BA2 addressing
Or whatever else that will work at this point

The contradiction between the documentation stating "3 bank signal lines" and the actual signals showing only SBA[1:0] is confusing.
Questions:
* Has anyone successfully implemented DDR3L with H6 (V200, not H616)? How did you handle the bank addressing?
* What's the proper interpretation of the H6 documentation vs the actual signals?
* Is there a reason why most projects go with LPDDR3 instead? Is this related to the bank addressing issue?
Any insights from those who've worked with H6 or similar situations would be greatly appreciated!
Thanks in advance!