If you have a synchronous clock, then it's trivial.
In the likely event that you don't have that, you would either need to do clock recovery or oversampling.
Since your data rate is fairly low, I would suggest to oversample the data to recover the bits.
Use a couple of flops to remove metastability from the synchronizing stage.
Then detect edges by comparing two consecutive samples.
Start a counter when you see an edge and measure clock cycles to the next edge.
Use a window comparison to figure out if you just saw a short or long pulse width.
If it was long then you saw a zero.
If it is short set a flag, unless the flag is already set in which case you detected a one.
Make sure to reset the flag when you see a zero as well and capture weird pulses as errors, which will help with debug.
You should aim to get at least three to four samples on the short pulse width, more is better, so the sample clock frequency should be above 4 MHz.
Easy to do inside a CPLD or FPGA.
You could also do this on a dedicated timer pin of an MCU, but you would be spending a lot of time in the interrupt routine and might not get much else done.
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