I thought I had issues with "multiple assignments" if I assigned where it was declared and then assigned it in an 'always' block, but I could be mistaken. Heck, I am sure I am mistaken because I trust that you know Verilog far better than I do!
Let me know if you get an error. There will probably be synthesis errors if you do another blocking assignment in an always block (inferring combination logic). Shouldn't be an issue with a non-block assignment for combination logic.
If you get time and use Vivado, look into SystemVerilog. It has some features from VHDL but retains some of the simplicity of Verilog.
I too try to avoid using global resets in FPGA designs as much as possible, but if I don't have initial blocks I end up with "X"s everywhere during simulations. For example, in this project I have to replace every 512th "Blank Start" symbol with a "Scrambler Reset" symbol, so have a 9-bit counter and look for it rolling over.
I don't care about the initial value of this 9-bit counter, but unless it is given one it stays at "all Xs" forever, making the simulation and h/w not match. Mismatches are bad, so at least for now I am working with an "initialize every reg" mindset.
If you want to looked any any register in simulation, you must initialize it. per the Verilog spec, all registesr start as "unknown". Unforunately, you have to initialize anything you want to monitor. It just becomes a habit.
You can also initialize internal registers from you simulation test bench. Let's say your module call "Foo" in your test bench has an internal reg "Bar". You might instantiate it in your test bench like this:
reg ClkIn = 0;
wire [7:0] OutputMonitor;
Foo U1 (.Clk(ClkIn), .Output(OutputMonitor));
In your simulation you can access the internal reg "Bar":
initial
begin
U1.Bar = 8'b101010101;
end
It is very useful for monitoring internal junk.
Speaking of "internal" simulation with Verilog... This trick I saw in the Picoblaze design using //synthesis translate_off //synthesis translate_on directives. You can create a "fake" string that only exists in simulation to overlay on your output diagram:
//This is useful for simulation purposes
//synthesis translate_off
reg [16*8-1:0] StateString;
always @(*)
begin
case(CurrentState)
`WAIT_FOR_BTN0: StateString = "WAIT_FOR_BTN0";
`WAIT_FOR_BTN1: StateString = "WAIT_FOR_BTN1";
`WAIT_FOR_BTN2: StateString = "WAIT_FOR_BTN2";
`WAIT_FOR_BTN3: StateString = "WAIT_FOR_BTN3";
`COUNT: StateString = "COUNT";
default: StateString = "Unknown";
endcase
end
//synthesis translate_on
endmodule
You could access this string from your simulation as U1.StateString
I haven't been doing FPGA for awhile and miss it now... Raw State machines and processing pipelines really get me interested! None of this Python and Javascript shit.
Nice work on getting the DisplayPort up and running. I may have to work that in the course I teach. We do experiments w/ VGA but it is getting harder for students to get access to monitors with a VGA port!