EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: Boomchil on April 28, 2024, 07:56:48 am
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Hi everyone.
I would like to divide a clock by 3 using an ATF16V8B, to clean the video signal of a Sega Master System 2 (to bypass the division made internally which creates noise in the RGB lines). I only have ATF16V8B and I'm struggling to find the code or even the tools to do it (I'm on MacOS).
I have found this VHDL code : https://www.asic-world.com/code/vhdl_examples/divide_by_3.vhd (https://www.asic-world.com/code/vhdl_examples/divide_by_3.vhd) so far but I can't find the tools to synthesis it to Jedec.
Can you please tell me if this is doable, and how could I do it ? I can access to a Windows computer if needed.
Many thanks for your help :D
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No, it's impossible.
VHDL code use triggers with positive and negative clock edges. ATF16V8B have only positive clocked triggers.
You can create simple divider by 3 on it, but you've got not symmetrical output (with duty cycle 1//3 or 2/3 - on your choice)
And for ATF you need a special programmer (hardware), do you need any?
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Does it has to be with a PLD?
For relatively constant Fin, a divider by 3 can be implemented with a HC74 D-type flip-flop and an LC, like this:
(https://www.eevblog.com/forum/index.php?action=dlattach;topic=399237.0;attach=1916802;image)
Found this unusual dividers idea from a PDF by Charles Wenzel (http://techlib.com/files/dividers.pdf), where a tuned LC is inserted in a typical D-type FF divider by 2, so to make it divide with ratios other than 2. :-+
Tried that once, to divide by 3 a 4.9152MHz TTL oscillator. It worked very well, stable and not picky to the exact LC values (as long as the LC values are not totally off).
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No, it's impossible.
VHDL code use triggers with positive and negative clock edges. ATF16V8B have only positive clocked triggers.
You can create simple divider by 3 on it, but you've got not symmetrical output (with duty cycle 1//3 or 2/3 - on your choice)
And for ATF you need a special programmer (hardware), do you need any?
I don't know if this is possible on the ATF16V8B but this code will divide by 3 symmetrically only on the posedge of the clk
It's a cheat where you make a counter count to 3 and mux the output between 0, clk and 1 so I get the symmetrically from the clk input
module clk_div_3(
input wire clk,
output reg out);
reg [1:0] cnt = 0;
always@(posedge clk)
begin
begin
cnt <= cnt + 1;
if (cnt == 2) cnt<= 0;
end
end
always@(clk)
begin
case(cnt)
2'b00 : out = 0;
2'b01 : out = clk;
2'b10 : out = 1;
endcase
end
endmodule
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Here's a divide-by-three:
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Can you please tell me if this is doable, and how could I do it ? I can access to a Windows computer if needed.
Yes it is doable, with the caveat you have a 1/3 or 2/3 duty as mentioned above.
You need Wincupl, to compile boolean equations to JED and then a Device programmer to pgm the 16V8.
WinCUPL can run command line, which may help portability ?
If all you are doing is /3, you could look at other CMOS programmable dividers ?
eg the widely available HC161/HC163 can divide by 3 with an upper Qn connected to /LOAD, so the counter goes 14,15,0,14,15,0... for divide by 3.
Addit: If size matters, you could find a small MCU that has a CLK out option with /3 choice. Still needs programming, but it will be smaller than a 16V8 or CMOS counter.
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I don't know if this is possible on the ATF16V8B but this code will divide by 3 symmetrically only on the posedge of the clk
It's a cheat where you make a counter count to 3 and mux the output between 0, clk and 1 so I get the symmetrically from the clk input
That could be done, with some caveats.
The 16V8 has no CLK in the product term array, so you need to join 2 input pins.
Generating a CLK from an async MUX like that, exposes the risk of a runt pulse, in the handover from MUX=CLK to MUX='1'
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Main problem with 16V8 not a possibility of implementing something with it, but possibility to program it. It requires special hardware to program, and programming specifications is not publicaly available (official).
So, if you do not have access to some PLD programmer using 16V8 is a very problematic
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Thank you all for your answers. I have a TL866II so programming it is not a problem, but reading your answers there doesn't seem to be any simple and reliable way to do it, so I've decided to source a dead Sega Master System 2 to get its VDP and use it as an external "divide by 3 only" module.
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Can you please tell me if this is doable, and how could I do it ? I can access to a Windows computer if needed.
Yes it is doable, with the caveat you have a 1/3 or 2/3 duty as mentioned above.
You need Wincupl, to compile boolean equations to JED and then a Device programmer to pgm the 16V8.
WinCUPL can run command line, which may help portability ?
If all you are doing is /3, you could look at other CMOS programmable dividers ?
eg the widely available HC161/HC163 can divide by 3 with an upper Qn connected to /LOAD, so the counter goes 14,15,0,14,15,0... for divide by 3.
Addit: If size matters, you could find a small MCU that has a CLK out option with /3 choice. Still needs programming, but it will be smaller than a 16V8 or CMOS counter.
double* and divide by 6?
number 4, http://xilinx.pe.kr/_xilinx/html/tip/sixeasypieces.htm (http://xilinx.pe.kr/_xilinx/html/tip/sixeasypieces.htm)