Electronics > Microcontrollers

Dividing 20MHz FPGA clock down to 2Hz

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amyk:
I like power-of-2 clock frequencies because it makes division much simpler. :)

codeboy2k:

--- Quote from: amyk on December 30, 2013, 07:12:42 am ---I like power-of-2 clock frequencies because it makes division much simpler. :)

--- End quote ---

Me too.  It also uses much less resources in an FPGA, for example the synthesizer can just use the single carry out from a counter chain as an enable line to the register that counts at the lower frequency.  It no longer needs to use LUT resources as a comparator, so those are free for other uses.

mrflibble:

--- Quote from: codeboy2k on December 30, 2013, 09:19:42 am ---
--- Quote from: amyk on December 30, 2013, 07:12:42 am ---I like power-of-2 clock frequencies because it makes division much simpler. :)

--- End quote ---

Me too.  It also uses much less resources in an FPGA, for example the synthesizer can just use the single carry out from a counter chain as an enable line to the register that counts at the lower frequency.  It no longer needs to use LUT resources as a comparator, so those are free for other uses.

--- End quote ---
Ditto. I also like numbers that have single multiplicities for the prime factors, where the prime factors are small enough that they fit nicely in a shift register (<= 16 or <=32). AND the outputs of those shift registers and voila, we have clock enable. Even cheaper in resources than carry chains. And less effort to get it working at high clock speeds.

djsb:
Thanks everyone for your help. I'll go back and change my code as suggested. Then I'll try and do some more reading on how all this stuff works.

David.

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