EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: Fantasma25 on October 25, 2013, 02:43:07 pm
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Hello. I'm trying to make a 4 bit calculator with a Basys2, but I'm having problems with the division. I've converted the input form std_logic_vector to unsigned, and I'm using the "ieee.std_logic_1164" and "ieee.numeric_std". In the simulation (with the student edition of Active HDL) it works beautifully, but when I want to sinthesize the code with the Xilinx ISE, it gives me this error refering to the line where I have the division.
Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2
Does anyone has ever had any problems with this?
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Makes total sense. You are trying to force an Integer logic block to make "floating point". If it is really 4 bit, you can just make the results by a table by calculating them by hand.
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Why not set up a counter to count the number of times you can subtract the divisor from the dividend.
If after subtraction the dividend is less than the divisor, your result is in the counter, the remainder being what's left of the dividend after all the subtractions.
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Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2
Does anyone has ever had any problems with this?
The / division operator is not synthesizable. So yes it simulates fine, and no you cannot synthesize it. Best bet is either use a LUT, or use some IP / core from your favorite vendor.
Edit: since you want only 4 bits, LUT (lookup table) seems to be the obvious choice.
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This is exactly the reason why I prefer the Altera boards more than the Xilinx boards... With the Xilinx ISE Design Suite I had the same problem and I had to do a work-around for dividing numbers. With the Altera Quartus II the division with / works just fine. I had the same problem also when I tried to make a function to find out the remainder of a division on the Xilinx software. When I made the same function on the Altera software, it worked fine without work-arounds...
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This is exactly the reason why I prefer the Altera boards more than the Xilinx boards... With the Xilinx ISE Design Suite I had the same problem and I had to do a work-around for dividing numbers. With the Altera Quartus II the division with / works just fine. I had the same problem also when I tried to make a function to find out the remainder of a division on the Xilinx software. When I made the same function on the Altera software, it worked fine without work-arounds...
You have pre-made blocks you can configure and use. I dont see the problem with that. They probably synthesize better.
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This is exactly the reason why I prefer the Altera boards more than the Xilinx boards... With the Xilinx ISE Design Suite I had the same problem and I had to do a work-around for dividing numbers. With the Altera Quartus II the division with / works just fine.
Very interesting, it's been some time since I've used Altera tools, my experience was positive (this was around 2005-2006). Mostly (90+%) using Xilinx tools. It seems that Altera has integrated a module generator for division; Xilinx would have you core-generate one I guess and the process would be manual.
I don't know if both X and A optimize for constant multiplications or divisions. Does anybody know?
There are known algorithms for strength reduction. For instance, I have implemented kdiv for division, it generates generic assembly and optimized C routine for divisions by integer constants. The result is a floored integer.
I also have a kmul based on suitable algorithms (Bernstein/Briggs).
See here for kdiv: http://sourceforge.net/projects/kdiv/ (http://sourceforge.net/projects/kdiv/)
It is licensed under BSD, so it is basically do whatever but attribute!
I also have complete support for these stuff in my high-level synthesis tool , HercuLeS (http://www.nkavvadias.com/hercules (http://www.nkavvadias.com/hercules)) but this is another story.
Best regards
Nikolaos Kavvadias
http://www.nkavvadias.com (http://www.nkavvadias.com)