As pcprogrammer says. it should be possible, given also the relatively slow SPI speed if used for WS2812 control (about 6.4 MHz if 8 bits per WS2812 "bit" are used, but it's probably possible to go lower using 4 bits/bit).
In an SDR home project with a iMX RT1021 we are simultaneously using two DMA channels for I2S in and out (up to 384 kS/s, L+R channels), one for SPI out at 45 MHz, and one for memory to memory moves at a handful of milliseconds interval.
If you are using the NXP SDK, and especially with freeRTOS adapted drivers (not sure you are using it), there's a lot of overhead.
I have stripped the drivers to the bare minimum, building your own TCD (transfer control descriptor) and using direct register access will ease the CPU load a lot - the eDMA controller in this series is not outlandishly difficult to use.
Also, remember to check what is the best priority grouping and scheduling algorithm for your use case to avoid channels starving each other (should not happen, given the speed).
Eta: WAIT! isn't the FlexSPI used only for the external flash? I'm not sure you can use it (at least, this is on the 1021).
Still, you have three FlexIOs that can be repurposed to SPI - or something more WS2812 friendly, maybe.