I don't think so? Placing decoupling caps very close to STM32 VDD plus a 100MHZ choke should filter it all.
For example, how would you propose to deal with emissions that are radiated along GPIO pins?
Consider the equivalent circuit:
(Core switching at 480MHz + harmonics) --- on-chip capacitance --- residual noise through VDD and GND pins
jointly --- board VDD/GND plane.
GPIOs connect to internal VDD/GND somewhere on the "on-chip capacitance" node. The package pins, wire bonds, etc. introduce some impedance between this reference plane and the PCB reference plane. There will be some common mode appearing on every pin, even if (especially if!) they are assigned static VDD/GND (or Hi-Z, through output stage capacitance).
There is also some spreading resistance on die (probably pretty low, they use either multiple metal layers, or solid planes at least, to keep resistance and inductance low, and capacitance high), so we might further expect some variation between GPIOs. That is, if you measure the noise between a given pair of GPIOs both set low (or high, or even set opposite for that matter), how much will depend on whether they're in the same IO bank, or not, or on entirely opposite sides of the chip.
The exact pin to board impedance will matter some, too, of course. Since that contributes to the gradient voltage across the die.
In any case:
the AC voltage drop on the supply and ground pins provides a route for common-mode emissions through all other pins of the chip.Now, VDDCORE won't be VDD pins directly. It is on slower, simpler chips, but, well, being slower they also have less harmonic emission for example. These, use an onboard 1.2V or whatever regulator (sometimes a bulk capacitor is required on an exposed pin; I don't recall offhand which STM32s do, if any), so there's additional opportunity for bypassing (i.e. internal VCORE
and internal VDD have onboard capacitance available to them). Moreover, the 480MHz signals are routed within the core area, and only fractions thereof are routed to the actual IO banks, and GPIO pins in turn. Generally the core is, well, at the core (center), and IOs are dotted around the edge. The high voltage IO domain doesn't switch as fast (fractional to several ns), so there will be less harmonic content, though the signal level of course is higher too.
And further details still, which will both provide further opportunity for emission, and further reduction in level; the full picture is the sum of all contributions. I'm only roughly assuming a few of them in the above here. But this is all just to say -- it's not something you can sprinkle ferrite beads over and say "done".
Or, to put it another and much simpler way: what's so goddamned special about VDD, it's CMOS, it's the same upside-down isn't it? Anything we should filter VDD to, we should equally well filter GND to. Why not?
Well, we again get a hint from VCORE being a thing; there must be level translators inbetween supply domains, and they've presumably defined a common ground (substrate), which therefore makes that GND more special than one VDD or the other. Maybe not to the external circuit (PCB) if core is entirely internal (all we see externally is the overall chip reference plane, whatever that is -- presumably somewhere intermediate between GND and VDD). Or, any ICs with defined input thresholds, independent of supply (not sure about logic families, but many interface ICs have e.g. a TTL/LVCMOS input threshold for any operating VCC/VDD), they might be using a common-source NMOS to define that threshold, in which case noise margin would be worsened with GND filtering, i.e., GND is a particularly privileged node in that case.
So we probably don't want to filter ground, or at least very much, and in general. Perhaps there are special cases where we would. But we still update our perspective based on such thought experiments. We might figure that, if we need low jitter for example, we should probably just try not to do very much else with a given IC (anything that would draw interfering currents through its supply/GND pins and thus contribute to time error in logic thresholds); or for especially low radiation, we probably want to add filtering to any output pins, maybe inputs too.
Which is fairly trivial as advice goes, as you don't really want naked GPIOs touching connectors, but some RFI filtering and ESD protection usually, and that confers improvement in both immunity and emission.
But if we're talking 480MHz and harmonics, there's not much we can do about that at board level, about the chip itself -- given that it's a significant fraction of a wavelength across. For that, we are at the mercy of whatever the emission limit is, and how well attenuated those signals are between CPU core and pins.
Which, observationally, no one is having a tremendous problem with this, so it seems we can expect they've done a reasonable job on-chip. But keep in mind what that means:
commercial levels are probably fine. Do pay attention if a project has exceptional limits, say an extra 20dB stricter or worse. Shielding will most likely be necessary in that case; perhaps as simple as a ferrite plate over the chip, perhaps a metal can, perhaps a metal enclosure altogether.
Which also means we can relax our circuit design, at least a bit, at least with respect to this particular concern (fast internal clocks). Sprinkling ferrite beads indiscriminately is as likely to make things worse as better; but just following a normal orderly, plane-based design process is likely to result in good success, and at least a fine starting point for further reduction if necessary (like, having a reference plane to attach shields to).
Tim
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