Author Topic: do you know a pretty VHDL & Verilog code beautifier ?  (Read 6402 times)

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Offline legacy

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do you know a pretty VHDL & Verilog code beautifier ?
« on: September 25, 2013, 08:19:33 pm »
for C sources i am used to invoke dev-util/uncrustify, which is able to make my source code prettier about indentation
wandering if there is something similar to beautify  VERILOG & VHDL's sources.

thanks  :scared:
 

Offline c4757p

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Re: do you know a pretty VHDL & Verilog code beautifier ?
« Reply #1 on: September 25, 2013, 08:24:08 pm »
Just use a proper editor that has auto-indentation... Out of the ones that you probably don't want to use... I regularly use vim and emacs, both of which will do this with damn near any source language, and given their age, I'm sure you can find a "modern" editor that does the same.
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Offline legacy

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Re: do you know a pretty VHDL & Verilog code beautifier ?
« Reply #2 on: September 25, 2013, 08:52:19 pm »
it seems there is a VIM script for VHDL
 

Offline legacy

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Re: do you know a pretty VHDL & Verilog code beautifier ?
« Reply #3 on: September 25, 2013, 08:53:43 pm »
 

Offline legacy

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Re: do you know a pretty VHDL & Verilog code beautifier ?
« Reply #4 on: September 25, 2013, 09:01:34 pm »
has anybody tried Sigasi ? In case, what do you think (it is much more than a beutifier)
 

Offline mrflibble

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Re: do you know a pretty VHDL & Verilog code beautifier ?
« Reply #5 on: September 26, 2013, 01:00:38 am »
has anybody tried Sigasi ? In case, what do you think (it is much more than a beutifier)

If you use VHDL then sigasi is definitely worth trying. It does have some handy features. Too bad they don't do systemverilog. :P
 


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