Author Topic: How to measure the performance of an algorithm, using Keil Virtual hardware  (Read 813 times)

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Offline ali_asadzadehTopic starter

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Hi,
Regarding this thread,
https://www.eevblog.com/forum/microcontrollers/converting-to-cortex-m0-asm/
I managed to port the MP3 library to Cortex M0, But In this link I have used Keil simulator to measure the required clock cycles to decode a MP3 frame, to my surprise I find that the Cortex M7 requires much more clocks than M4, so maybe the keil simulation is not accurate, so to be able to re-measure  it again on M0,M3,M4,M7 I should test them on an ARM VHT, which ARM claims that are very accurate,
So I have started a new project with Arm Virtual Hardware Target , But I have some problems in Compiling and running the simulation, That's where I need your help.
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But the project fails to compile
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I have attached the keil project, I'm using the community version of it.
So the first step is to be able to build and debug the code.

I have tried to replace add the Cortex M0 start up from another working project, But it would make it worse, with a lot more errors!
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Offline cgroen

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Do you have a linker file (.sct file) in the project ?
It seems that the stack area is not defined for the linker

(below is a random copy of one of my sct files, which might be totally unsuited for your use, but just to give you an idea)

Code: [Select]
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c
//----------------------------------------------------------------------------
// PIPIApp-small.sct 20210721 CHG                                                 
//
//----------------------------------------------------------------------------
// Scatter file for PIPI application
//----------------------------------------------------------------------------

#define m_text_start                   0x000A0040 // 640 from beginning of internal Flash
#define m_text_size                   (0x00200000-m_text_start) // Max 1408 KByte

#define m_data_start                   0x20040000 // SRAM 256 KByte from beginning (first 256 KByte reserved for FW)
#define m_data_size                    0x00040000 // Max 256 KByte for PIPI application

#define Stack_Size                     0x0000 // Set stacksize to 0 as we use the stack from FW or from our own thread stacks
#define Heap_Size                      0x4000

LR_m_text m_text_start NOCOMPRESS { ; load region size_region
 
    ; CHG 20220224 Used to be:
    ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
;ER_m_text m_text_start m_text_size { ; load address = execution address
* (.PIPISTART, +FIRST)
* (InRoot$$Sections)
.ANY (+RO)
}

RW_m_data m_data_start m_data_size {
.ANY (+RW +ZI)
}
 
ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
}

    ; Place (non existing) stack in SRAM
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
}



« Last Edit: June 20, 2022, 02:00:24 pm by cgroen »
 

Offline ali_asadzadehTopic starter

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It does not need the .sct file, since it's using the memory layout target!
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Offline cgroen

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Have you looked in the "objects\test.sct" file ?
 

Offline ali_asadzadehTopic starter

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cgroen, I have attached the keil project in the first post, please try to download it, maybe I'm missing something, so you can try to see if you could find the solution, thanks for your help.
ASiDesigner, Stands for Application specific intelligent devices
I'm a Digital Expert from 8-bits to 64-bits
 

Offline cgroen

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cgroen, I have attached the keil project in the first post, please try to download it, maybe I'm missing something, so you can try to see if you could find the solution, thanks for your help.

As I wrote, check the test.sct file. There is no STACK assignment in that one.

I added this to the file, and it now links
(You have to CHANGE the values and addresses, I just used some arbitrary numbers.....)


Code: [Select]
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m4 -E -x c

; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************

#define m_data_start                   0x20040000 // SRAM 256 KByte from beginning (first 256 KByte reserved for FW)
#define m_data_size                    0x00040000 // Max 256 KByte for PIPI application

#define Stack_Size                     0x0400 // Set stacksize to 0 as we use the stack from FW or from our own thread stacks


LR_IROM1 0x00000000 0x00400000  {    ; load region size_region
  ER_IROM1 0x00000000 0x00400000  {  ; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
   .ANY (+XO)
  }
 
  RW_IRAM1 0x20000000 0x00400000  {  ; RW data
   .ANY (+RW +ZI)
  }
 
  ; Place (non existing) stack in SRAM
  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
  }
 
 
}


 

Offline ali_asadzadehTopic starter

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cgroen thanks for the update, Would you please attach your working project, I have added these to the project, and it's not working :palm:
ASiDesigner, Stands for Application specific intelligent devices
I'm a Digital Expert from 8-bits to 64-bits
 

Offline cgroen

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Attached

 

Offline ali_asadzadehTopic starter

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Thanks cgroen
ASiDesigner, Stands for Application specific intelligent devices
I'm a Digital Expert from 8-bits to 64-bits
 


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