When they were asking the community about more features or upgrades to a next gen chip they got a lot of suggestions.
a few have been included.
However they did say that putting a HS phy in the chip would ahve taken a very large area of silicon compared to the FS phy. So their engineers opted for that instead. I tried to convince them to at least implement a ULPI interface like on most higher end ST chips, but it looks like they didn't end up doing that.
As far as the ADC, lots of user requested a better performing ADC, that was much more linear, so I'm hoping they have improved that.
It does suck that they have removed bluetooth, at least for my use case. However i will be the first to admit, having ble capability in the chip, but then having the minimum power consumption with bluetooth on of ~15-20mA (thats what it curretly is) isn't super ideal.