External crystal required for low speed USB on CH32V203?

[eigenvektor]

Sorry if this is a noob question but I just wanted to make sure,
the datasheet for the CH32V203 mentions a "Built-in factory-trimmed 8MHz RC oscillator" and a "Built-in PLL, optional CPU clock up to 144MHz", but no mention of tolerances. The datasheet also does not specify anything about crystalless USB.
Do I need to an external crystal if I only plan on using low speed usb (HID input device keyboard)? I have attached the datasheet.

[brucehoult]

USB low speed needs a clock accurate to 1.5%.

According to table 4.3.6 the internal oscillator is accurate to within -1% to +1.6% between 0ºC and 70ºC.

So it should be ok.

Many devices take advantage of USB's 8b/10b encoding that guarantees a limited maximum time between level transitions to lock onto the USB clock by PLL or digital oversampling. IN that case you don't need a well calibrated clock at all. I didn't find any mention of this.

[eigenvektor]

Ah yes you're right, I overlooked that. Thanks!

[voltsandjolts]

If you want to avoid crystal for mechanical shock reasons, you could use a resonator for low speed.

Data Signalling Rate

Another area which is often overlooked is the tolerance of the USB clocks. This is specified in the USB specification, section 7.1.11.

    High speed data is clocked at 480.00Mb/s with a data signalling tolerance of ± 500ppm.
    Full speed data is clocked at 12.000Mb/s with a data signalling tolerance of ±0.25% or 2,500ppm.
    Low speed data is clocked at 1.50Mb/s with a data signalling tolerance of ±1.5% or 15,000ppm.

This allows resonators to be used for low cost low speed devices, but rules them out for full or high speed devices.

https://www.beyondlogic.org/usbnutshell/usb2.shtml#DataSignallingRate

[eigenvektor]

No just trying to save cost and board space, but I found ones for 10ct in 2x1.6mm so might throw on a crystal to be on the safe side.

[newbrain]

Many devices take advantage of USB's 8b/10b encoding that guarantees a limited maximum time between level transitions to lock onto the USB clock by PLL or digital oversampling. IN that case you don't need a well calibrated clock at all. I didn't find any mention of this.

There's this in the RM, in chapter 21.1 Main Features of the USBD section:

* Frame locked clock pulse generation

It might be related to some kind of self synch, but I could not find much else.

[eigenvektor]

Ouh that is actually very interesting information I was completely missing in the datasheet specific to the CH32V203, thank you very much :)
I was wondering how come that one was so sparse of information.

[eigenvektor]

From the reference manual (see attachment)
There seems to be a "USB HS PLL" present providing 480 MHz, although I'm not knowledgeable enough to make any conclusions from that...
Edit: this is actually for the CH32V305, for the CH32V203 see the second attachment. Reading is a useful skill sometimes.

[brucehoult]

Knowing what to look for helps too.