DAP does not need the performance, so yes, I would not expect multi-core stuff to matter.
USB HS is the critical part. FS limits the speed at 64 KByte/sec and really bad turnaround time.
Yes of course. Since it's HID, yes it tops at 64 KBytes/s in FS. I don't remember in HS if there's a lower limit for HID or if you can get the full throughput, but either way, it's much faster.
And of course, you don't need a powerful MCU to handle DAP. You just need one that can be clocked fast enough so that the serial clock will be high enough.
As a quick calculation, if it uses SPI or similar for the JTAG/SWD interface, you may typically need a peripheral clocked at a multiple of the max serial rate (2, or 4 times is typical), so, for a 30MHz link, for instance, you'll need a peripheral clock of 60MHz or 120MHz. Depending on the architecture, the core clock will be required to be at least this fast as well. So, a MCU running at > 100MHz actually makes sense for a fast DAP link. Multiple cores, OTOH, are likely completely useless. Anyway, CMSIS-DAP implementation is open and usually what is used on those boards, and I don't think it supports multi-core anyway.
The Link2 probably uses this particular chip because they use it on some other dev boards as well.