Thank you, Siwastaja, Kleinstein and brucehoult, for your interesting practical ideas.
For instance, I have to use ATmega8 in my products to minimize their cost and let them be competitive in the local market.
In designing AC meters, I usually use the time-division topology.
The period of the main loop is fixed. It is the ADC reading time in the free running mode (13 ADC cycles).
When the ADC interrupt flag is set (the starting point of the main loop), a start common code is executed which ends by IJMP; a jump to the address in ZH:ZL which is incremented continuously and reset when the external interrupt flag is set (that signals the end of the main’s cycle).
After IJMP, one or more functions could be executed and end with an AJMP; to jump to the end common code before returning back at the start of the main loop.
If the MCU crystal is 8 MHz and the ADC prescaler is 64, the ADC reading time is 832 cycles (64*13) and 104 us (1/8*832). In this case, The IJMP list (of RJMPs) should be longer than for one main's cycle (for simplicity, I usually make it 256 long for which the lowest frequency is about 38 Hz). In case of 50Hz, the number of samples is close to 192 (20ms/104us). Also, to simplify the sensor circuit, I pass just the half cycle (current or voltage). The worst case is when the signal peak at the ADC input equals the ADC reference when the reading is 1023 (10-bit ADC). By using Excel, the sum of the ADC readings of the half cycle could be found to be close to 52326448 (0x031E7030). And, in case I read, during this half cycle, both the voltage and current, this sum becomes 26163224 (0x018F3818) which, as we see, has to be saved in 4 bytes (a 32-bit register). Obviously, this number increases when the frequency decreases.
By the way, in this case, the divisor could be expected, speaking practically, to be any number between 174 (about 55 Hz) and 214 (about 45 Hz).
But on my 1st post, I assumed that the divisor could be between 320 and 447. Actually, this was for the case when the ADC prescaler is 128 (416 cycles, 52us). Also, it was for the highest frequency 60 Hz (1/320/52us) and the lowest one 43 Hz (1/447/52us). The AJMP's list (for IJMP) had to be doubled.
I mean; I made a mistyping on my 1st post because 132 cycles (+ 7 cycles for ACALL and RET) is for the case of ADC timing of 104us. I had to write 145 cycles instead, which are for the case of 52us.
Naturally, in both cases, the division is faster if rounding is not important; 99 and 103 cycles respectively.