Very simple Logic Analyzer DIY

[conducteur]

I Don't want to buy a logic analyzer, or a new oscilloscope, but sometimes (like now), i'm in a situation where I need to monitor multiple TTL signals.
So I'm trying to build one DIY-style. I don't aim to achieve high frequencies. My goal is to achieve te highest possible bandwith with the hardware that i already have
(often i can drive the  circuit at a much lower clock frequency to test it).

I grabbed my Easypic v7 devboard from Mikroe with a PIC18f45k22. This thing has a 4x PLL and a 16MHz internal Oscillator. The PIC runs on 64Mhz. This means that 16 million instructions can be executed in a second.  People are now screaming at me that i should use a FPGA or something like that, but that's maybe something for a future project. First try with the things that i have now. (a pic devboard, a pc....-

The best display i have is... my pc, I want to learn how to write a program that displays the waveforms.
I am a bit familiar with Java for simple programs, but maybe i'll try to do it wit c#.NET. I still need to do some research how to create waveforms in such a program.   If anyone can help me with this?

So far so good, i created a little program in JAL (just another language), that reads the µc PORTD and sends it over the usb-uart to my laptop.
This program works just fine, in a terminal window (putty), i see  the numbers representing the signals at the corresponding pins on the pic.


one thing that makes me worry is that i can't achieve high baudrates? Is a PLL/INTOSC such an unstable clock that it will generate rubbish at 115200 baud?
I'm now stuck at 2400 Baud. (maybe a bit higher should work, but at 9600 things start to go wrong). 

Can i enhance the baudrate in a way that it still is reliable and doesn't generate rubbish when having a look at the data in putty terminal?

[Alex Eisenhut]

It might not be the stability, but the divider can't get close enough to a standard baudrate with the clock frequency you have.

Please check that first.

[rs20]

It might not be the stability, but the divider can't get close enough to a standard baudrate with the clock frequency you have.

Please check that first.

Clarify? Are you saying that 115200 baud can't be generated by dividing down a 16 MHz clock?

[mikerj]

It might not be the stability, but the divider can't get close enough to a standard baudrate with the clock frequency you have.

Please check that first.

Clarify? Are you saying that 115200 baud can't be generated by dividing down a 16 MHz clock?

Correct, you can't get 115200 by dividing 16MHz with an integer value.  This is why you often see 'odd' frequencies used such as 7.2838MHz, as you can get an exact baud rate.

16MHz is particularly problematic for 115200, since the resulting baud rate error is high enough that problems can be expected.

[rs20]

OK, thanks. But with the OP having trouble attaining 9600 baud, I think that's not the issue since there's plenty of scope to hit 9600 very accurately?