FPGA Advice wanted.

[nctnico]

You probably will be able to download ISE 14.7 a century from now. It still will be available and if you have a computer that will run a 100 year old OS, you will be able to fire it up. There will not be anybody to call up when you have a question or find a bug.

It is the same as every new version of Windows: wait until the first service pack is released before trying and until the second service pack is released before using it for anything serious. ISE in it's current form has been around for over a decade and AFAIK the more recent versions are mostly introduced to support new devices. Sure at some point you'll want to move to Vivado but I'd rather wait for a couple of years. If I run into a problem with Xilinx ISE there are tons of answers in various fora and applications notes so no need to spend days to figure out whether you are doing something wrong or it is a missing feature/bug.

[Dubbie]

Thanks for all the input. I think I will continue with vivado. In the past I've always found it worthwhile to jump on board the train of the future, even if the first couple of years have a few wobbly bits and missing features!


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[Kilrah]

But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.

I'm starting right now with a Zynq on Vivado, and given the complexity of these tools I'd find it to be a waste of time to spend days/months getting used to an obsolete tool, when the new one has been around for >3 years already...

If there was a huge price difference that made the old chips that are not supported in Vivado that much more attractive why not, but they understood well enough that they had to avoid that and facilitate access to newer devices if they want to sell them AND get people to move to the new tools.

[uncle_bob]

As much as Xilinx would want it ISE isn't going to be obsolete for the next couple of years. There is still too much not working right in Vivado.

Hi

I've seen this process before. As much as the new super version has issues (they always have issues) ... they do go ahead and kill the older version. I'm not in any way saying that's right. It is what happens. If you get a couple of years of overlap that's better than the way some places do it. They *have* to get rid of the cost of support on the older version. A number of people's bonus plans depend on it. That's what makes it happen.

Bob

I think Xilinx is pretty up-front about the fact they no longer support ISE but what are they going to do, leave millions of projects with no support whatsoever?  That's not a winning strategy.

Their view is that they will leave 14.7 out there to support the devices in the field and move on to Vivado with just the slightest overlap in devices.  I don't see 14.7 going away, ever...

If they did kill off 14.7, how would they redefine 'field upgradeable'?  I think having a copy of the old version 10.x is pretty handy as well.  I still have Spartan 2 devices to program.

Hi

You probably will be able to download ISE 14.7 a century from now. It still will be available and if you have a computer that will run a 100 year old OS, you will be able to fire it up. There will not be anybody to call up when you have a question or find a bug. The latest and best timing info will be in other programs (even for the old parts). That is likely OK for a project you did 100 years ago and simply want to do a small tweak on. Available is not the same as supported ....

Bob

True enough.  The thing is, Xilinx has no intention of supporting legacy devices with Vivado.  Even chips as new as the Spartan 6 aren't supported in Vivado.  Nor do I expect them to ever incorporate the legacy devices.  They have a plan for moving forward and it works for me.  I can use the old software to support my older projects and I can use the new software with my newer projects.  But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.

If not, the Arty Artix 7 board is pretty nice as is the Digilent Basys 3.  In fact, the Artix would handle this job pretty well:
http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/

Mount a little mezzanine board on top for connecting the inputs and the rest is ready to go.  This board works well with Vivado.

Hi

Yup, The Trenz 725 is a Artix-7 board that can easily mount on an application specific board. That's what the OP went with. It's a pretty rational little chip with enough cool features to spend lots of time playing with.

Bob

[uncle_bob]

The OP wants a shitty FPGA that samples 16 pins at 60Hz, and now it has derailed to ISE vs Vivado ...
OP: If you do not want to use iceCube2, you can try PSoC. Still more than enough for your need. But I still recommend iCE40.
The smallest iCE40LP384 does have a QFN32 package and I believe I can write code to make it a synchronized SPI IO expander for less than 30 lines.

Hi

Back up and re-read it. He wants 10 nanosecond samples. The data comes out at a 60 Hz rate. That isn't going to happen with a PSoC.

Bob

[uncle_bob]

Back up and re-read it. He wants 10 nanosecond samples. The data comes out at a 60 Hz rate. That isn't going to happen with a PSoC.

PSoC devices have DSI interface, which allows async IO input directly into PLD fabric. Maybe not 16 channels, but 8 channels is easy, and you can use 2 chips to get 16 channels.
DSI input latch can also be used with an external clock, which even further reduced PLD fabric delay mismatch.

Hi

You need 16 counters that *async* clock at 100 MHz ... not going to happen on a PSoC. All the data and "clocks" are re-done against the CPU clock. That makes it a really rotten thing for precision timing.

Bob

[rstofer]

Hi

Yup, The Trenz 725 is a Artix-7 board that can easily mount on an application specific board. That's what the OP went with. It's a pretty rational little chip with enough cool features to spend lots of time playing with.

Bob

And a JTAG programmer?  I don't see an onboard USB->JTAG gadget so I suspect there needs to be something else at that JB1 header.
I like the 'stamp' format for boards.  Lots and lots of IO pins.

[uncle_bob]

Hi

Yup, The Trenz 725 is a Artix-7 board that can easily mount on an application specific board. That's what the OP went with. It's a pretty rational little chip with enough cool features to spend lots of time playing with.

Bob

And a JTAG programmer?  I don't see an onboard USB->JTAG gadget so I suspect there needs to be something else at that JB1 header.
I like the 'stamp' format for boards.  Lots and lots of IO pins.

Hi

He bought the programmer before we even got to talking about that part of it.

Bob

[uncle_bob]

You need 16 counters that *async* clock at 100 MHz ... not going to happen on a PSoC. All the data and "clocks" are re-done against the CPU clock. That makes it a really rotten thing for precision timing.

Data path and clocks are not synced if you do not want to do so. That's where DSI and HSIOM kicks in.
As for the counter part, who cares about relative phase shift against master clock? The OP only cares about <10ns jitter and <10ns channel skew. With async logic, it can be easily done.
PS. I'm referring to PSoC 4200 family, as I'm now working on it.

Hi

From the PSoC 4200 data sheet:

Maximum clock frequency anywhere: 48 MHz. That's < half of the 100 MHz he needs for 10 ns

Max macrocells per channel 8: If he did have 100 MHz, he needs more like 20 to 27 per channel, more likely 2X that if he wants it buffered.

It is a fun little part. It's  not a universal solution to all problems ....

Bob

[Sal Ammoniac]

If this is a start from scratch / I know none of them sort of thing - VHDL is what I'd pick.

Why VHDL? Any particular reason to choose it over Verilog or SystemVerilog?

[Dubbie]

Evb, I have all that info clearly defined. There are a couple of other little wrinkles such as 3bits of info encoded into the start pulse that I am going to have to time as well. As I mentioned, I am very new to programmable logic, so I expect that even if I fail at this project, I will learn a lot.


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[uncle_bob]

If this is a start from scratch / I know none of them sort of thing - VHDL is what I'd pick.

Why VHDL? Any particular reason to choose it over Verilog or SystemVerilog?

Hi

Pretty much everybody I know uses VHDL over the Verilog empire.

Bob

[Sal Ammoniac]

Pretty much everybody I know uses VHDL over the Verilog empire.

That's a quite personal (and very valid) reason to choose VHDL. Having others around you who are familiar with a language is certainly a big help, especially for beginners.

Let's assume an FPGA beginner wants to learn Verilog or VHDL, but doesn't have anyone around who knows either one. Which one would you recommend he choose? Why?

[nctnico]

Pretty much everybody I know uses VHDL over the Verilog empire.

That's a quite personal (and very valid) reason to choose VHDL. Having others around you who are familiar with a language is certainly a big help, especially for beginners.

Let's assume an FPGA beginner wants to learn Verilog or VHDL, but doesn't have anyone around who knows either one. Which one would you recommend he choose? Why?

I'd go for VHDL because it is much more a programming language and thus offers many powerful features to do a lot with only a few lines of code (creating designs which can be changed with just a few parameters is one of them). Also strong typing helps to avoid errors. Ofcourse an FPGA developer should know what HDL is going to look like in logic after the synthesizer is done with it but that doesn't mean a HDL developer should be describing the logic itself.
Having other people around who know 'X' doesn't sound like a good idea because you'll also inherit their bad habbits. When I started working with FPGAs the rest of the team used schematic entry and never heard of timing constraints. Even back then I made reconfigurable designs so when a design needed to scale up from 16 to 24 and later to 96 channels all I needed to change was a number. That was just beyond imagination with schematic entry.

[uncle_bob]

Pretty much everybody I know uses VHDL over the Verilog empire.

That's a quite personal (and very valid) reason to choose VHDL. Having others around you who are familiar with a language is certainly a big help, especially for beginners.

Let's assume an FPGA beginner wants to learn Verilog or VHDL, but doesn't have anyone around who knows either one. Which one would you recommend he choose? Why?

Hi

I would go for VHDL simply because it's what he is (in my limited sample) most likely to run into in the future. I realize this is a Ford / Chevy discussion that can go on for a few hundred years. To fully answer the question, somebody would have to be fully proficient in both and regularly use both for major projects on the same hardware. People are rarely that complex. They pick one and go with it. It becomes the default answer to the question ... In most cases that I've seen, they don't make the choice. They walk in and the place uses one or the other. They go with the "default language" or find work elsewhere. After a bit they become "centric" in one or the other and that tends to dictate where they go and what they do. Does it work that way 100% of the time? Of course not. It works that way in more cases than not. People do transition from one to the other. When they do, the "old one" does not get used. They can compare one "as it was on that project back then" with whatever they are using now. That tends to be a skewed comparison. Older normally = simpler.

Bob

[rstofer]

As Bob said, it's kind of a personal decision.  When I first started, the tutorials were written in VHDL and I have been using it ever since.  I just don't 'get' Verilog.  I have tried a couple of times to create a design with Verilog, gave up and returned to what I know.  That's not a criticism of Verilog, a whole lot of people use it.  Clearly, it works.  And, truthfully, I didn't really give it a chance.  It's not like VHDL flowed from my mind to the keyboard the first day either.

There are a few 'standard' things to know:  How to create a MUX, how to create a Decoder and, most important, how to create a State Machine.  There are a couple of lesser used things like the Priority Encoder but, basically, there are only a handful of constructs.  There are a number of tutorials on the Internet and I think "RTL Hardware Design Using VHDL" (Pong P. Chu) may turn out to be the best book I have on the subject.  But it's too expensive!  Maybe some of these:
http://www.alibris.com/booksearch?keyword=vhdl

So, sit down and spend the time to create small sample projects creating these blocks and really understand how they work.  Make sure there are default values for all the output signals in the state machines and everything will start to flow.

[Dubbie]

I am measuring the timing of externally generated pulses. There is a start pulse defined by its length, then a second much shorter pulse anything up to about 8ms later.
It is highly likely that several channels could have identical timing, so there is no time to do things serially


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[Chris Mr]

For what it's worth I have been using iCE40 for about three years now.

I use ISE to synthesise and simulate and then iCECube2 to get it on the chip.

I can thoroughly recommend "Advanced Digital Design with the Verilog HDL" book but it's expensive (£150).  There are three words in the preface...

Simplify, Clarify and Verify

That pretty much sums it up for me - so only £50 per word 

My big lesson was to only put on the FPGA that which _has_ to be there; if a micro can do it, put it in the micro.  So I simplified the FPGA, clarified that it would still do the job and then verified it.

One really nice feature of the iCE40 is that there is an SPI interface which is used to write the 'image' to the device (same port is used to program the non-volatile on-board memory when you want to finalise the design), and when you are testing that can come from a local micro.  Then, when the FPGA is running, those SPI pins can be used to interface to your design (pins programmed to be SPI of the FPGA design) via your local micro.  For quite a lot of things it's like having an FPGA with a micro on board.  One thing I really like is using the SPI as an I2C "global" interface.  The LE line becomes SPI / I2C select so when low it's an SPI port, high I2C.  The SPI clock becomes SCL and data send is MOSI, the data return being MISO.  You can then connect a load of I2C devices to different pins on the FPGA (to save PCB layout headaches) and just AND all the SDA pins when LE is high

The other thing is, I have been clocking the iCE40 with a CDCE925 which will go up to 230MHz (the CDCE that is) and whilst I have only been running it at a tad under 200MHz it is completely solid.  That's after temperature cycling and so on.  That allows you to use an ARM with an SPI running at 42Mb/s which is pretty cool.

Needless to say I am a fan of iCE40 

[sporadic]

For what it's worth I have been using iCE40 for about three years now.

I use ISE to synthesise and simulate and then iCECube2 to get it on the chip.

I can thoroughly recommend "Advanced Digital Design with the Verilog HDL" book but it's expensive (£150).  There are three words in the preface...

Simplify, Clarify and Verify

That pretty much sums it up for me - so only £50 per word 

My big lesson was to only put on the FPGA that which _has_ to be there; if a micro can do it, put it in the micro.  So I simplified the FPGA, clarified that it would still do the job and then verified it.

One really nice feature of the iCE40 is that there is an SPI interface which is used to write the 'image' to the device (same port is used to program the non-volatile on-board memory when you want to finalise the design), and when you are testing that can come from a local micro.  Then, when the FPGA is running, those SPI pins can be used to interface to your design (pins programmed to be SPI of the FPGA design) via your local micro.  For quite a lot of things it's like having an FPGA with a micro on board.  One thing I really like is using the SPI as an I2C "global" interface.  The LE line becomes SPI / I2C select so when low it's an SPI port, high I2C.  The SPI clock becomes SCL and data send is MOSI, the data return being MISO.  You can then connect a load of I2C devices to different pins on the FPGA (to save PCB layout headaches) and just AND all the SDA pins when LE is high

The other thing is, I have been clocking the iCE40 with a CDCE925 which will go up to 230MHz (the CDCE that is) and whilst I have only been running it at a tad under 200MHz it is completely solid.  That's after temperature cycling and so on.  That allows you to use an ARM with an SPI running at 42Mb/s which is pretty cool.

Needless to say I am a fan of iCE40 

I picked up an iCEstick two years ago learn FPGAs with and have yet to do anything with it.  Are there any good guides or tutorials for working with iCECube2 you could recommend?  I've found lots of good resources on VHDL and Verilog, as well as some decent tutorials for ISE and Quartus, but not so much for iCECube2.

[sporadic]

I picked up an iCEstick two years ago learn FPGAs with and have yet to do anything with it.  Are there any good guides or tutorials for working with iCECube2 you could recommend?  I've found lots of good resources on VHDL and Verilog, as well as some decent tutorials for ISE and Quartus, but not so much for iCECube2.

When you have a need to accomplish something, you will learn it automatically .

Haha, there's a lot of truth in that! That one's going in my quote book

[Chris Mr]

If you think of the iCEcube as a means to get the code formatted for the chip then all you really need is to do one project and that'll be it.

Essentially:
Once you have your synthesised code open up iCEcube and click on "new project".  It'll make a directory for it once you point it at wherever you want it to be (I usually put everything in a folder (Ver1 etc) and then the code is one folder higher up but its up to you.

Pick the device, package etc in the menu for new project and do "next"

Now pick your top level file (verilog in my case) and click the ">>" button so the file is added to the right hand side then click "finish"

Then you set the synthesiser tool by right clicking on "Synthesis tool" and set is to LSE.

Now you're good to go.  Click "Run Synthesis" and given that your code has already been tested it'll synthesise ok.

There is then only one more stage - you have to tell it which connection (from your design) goes to which pin which is in the "pin constraints editor".

Do that and then run "Run P&R" and it'll do the rest.

You get a .bin file in the directory under your original folder "\sbt\outputs\bitmap\<filename.bin>" which is just a binary so I wrote a simple "bintoarray.exe" that converts it into a 'C' array so your micro can include it in its code - and then send it to the FPGA (so you don't need any tools).


I thought that was going to be a couple of lines - a true optimist!

If you use ISE (xilinx tools which I am happy to do because I used lots of their parts in the past) to do the checking and synthesis - so your code has been checked first - there isn't much in the way between that and running it.

You are right though, it could do with a video 

[Dubbie]

Yeah, that last bit is where I came unstuck with the ice40! I couldn't figure out how to get the design uploaded. I thought it was pretty bad that the dev hoard doesn't come with a single working example. Anyway, I will start again with a more "normal" chip and VHDL in Vivado, and circle back later to the ice. I still think it will be the best for the job ultimately.


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[Dubbie]

Thats very generous of you Blueskull. Thanks!

[Dubbie]

I have the hx8k guess I'll figure out somehow what the led pins are


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[joeqsmith]

True enough.  The thing is, Xilinx has no intention of supporting legacy devices with Vivado.  Even chips as new as the Spartan 6 aren't supported in Vivado.  Nor do I expect them to ever incorporate the legacy devices.  They have a plan for moving forward and it works for me.  I can use the old software to support my older projects and I can use the new software with my newer projects.  But I would still recommend starting with a legacy device and the legacy softward if tutorials were of any concern.

If not, the Arty Artix 7 board is pretty nice as is the Digilent Basys 3.  In fact, the Artix would handle this job pretty well:
http://store.digilentinc.com/arty-board-artix-7-fpga-development-board-for-makers-and-hobbyists/

Mount a little mezzanine board on top for connecting the inputs and the rest is ready to go.  This board works well with Vivado.

I just bought this little eval board a few weeks ago and am setting up the software while I type.   I wanted to play with Vivado but the tool costs for my hobby use are out.  I had tried loading up the full tools when it first came out and ran various simulations.   I have used Foundation, ISE, MaxPLus and Quartus.  This tool set looked pretty nice the little I played with it, but no hardware to target.   This board comes with a full license but as I understand targets only this device.  No idea yet if there are other restrictions.   Read most of what I could find on-line about the board.   For $100, hard to go wrong if you just want to get your feet wet like me.

For home use, the part is way more powerful than anything I have played with.   Should be able to come up with something fun to do with it.