Electronics > Microcontrollers

FPGA Memory arbitration

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kd5pev:
Hello.
I am working on a project where I need to interface a microcontroller (AT90USB1286) with an FPGA (Spartan 6 lx9).

I currently have the AVR connected to the FPGA via the AVR's XMEM interface.
Inside the FPGA, this is connected to a dual port 65536x8 blockram (64 KByte).

Now, I want the majority of this RAM to be left to the AVR for its own purposes -- heap, stack, etc.
But, I want the FPGA to be more than a glorified SRAM chip; I want there to be a few memory mapped peripherals made from FPGA fabric.

Attached to this post is a general picture of what I want to do: ~48Kbyte of RAM for the AVR, and then 4 peripherals of 4Kbyte each.
My question is: how do I arbitrate access to the shared RAM to the peripherals?

Rufus:

--- Quote from: kd5pev on May 12, 2013, 12:38:38 am ---My question is: how do I arbitrate access to the shared RAM to the peripherals?

--- End quote ---

Don't think arbitrate is the right word but then not exactly clear what you are trying to do.

For what I think you are trying to do you just decode the AVR address bus providing a select signal for the RAM for addresses up to 48k and select signals for the 4k blocks above that. The select signals gate writes to the associated RAM or block and gate data onto the AVR data bus for reads.

kd5pev:
Thank you.
I think I was trying to make it more complex than necessary.
I tend to do that.  |O

What I was thinking of doing was:

--- Code: ---
AVR <-> RAM <-> Black box <-> Peripheral 1
                          <-> Peripheral 2
                          <-> Peripheral 3
                          <-> Peripheral 4

--- End code ---

What I got from your post was this:

--- Code: ---AVR <-> Address decoder <-> RAM
                        <-> Peripheral 1
                        <-> Peripheral 2
                        <-> Peripheral 3
                        <-> Peripheral 4

--- End code ---

Is that a correct interpretation?
If so, I think an address decoder would be much simpler to build than what I was originally going after.

Rufus:

--- Code: ---[quote author=kd5pev link=topic=16824.msg230961#msg230961 date=1368321522]
AVR <-> Address decoder <-> RAM
                        <-> Peripheral 1
                        <-> Peripheral 2
                        <-> Peripheral 3
                        <-> Peripheral 4

--- End code ---

Is that a correct interpretation?
If so, I think an address decoder would be much simpler to build than what I was originally going after.
[/quote]

In simplistic schematic terms yes. It is just the way microprocessors have always managed memory and peripherals on external busses.

kd5pev:

--- Quote from: Rufus on May 12, 2013, 02:08:00 am ---In simplistic schematic terms yes. It is just the way microprocessors have always managed memory and peripherals on external busses.

--- End quote ---

Okay, I think I understand that now.

Now this is more of a hypothetical question at this point:
How do I handle two (or more) components that want access to the same RAM module?


--- Code: ---Component A <-> |
                 <=> [ ?? ] <=> RAM
Component B <-> |

--- End code ---

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