Thank you all for your ideas and suggestions.
If you can find a microcontroller based hardware+software solution that is in a similar order of magnitude as your transfer rate
Actually we did manage to reach a writing speed of almost 15MBytes/sec using an ATMEL uC and a class 10 SD card. So I guess a configuration with an FPGA+2 micros+2 SD cards is possible but I'm still hoping there is a more elegant solution.
How is your data arriving ? you might be able to do it with no FPGA at the front end, or a simple CPLD. If, for example it's a parallel data stream, you can probably use timer/capture peripherals to grab every n'th sample. However routing a parallel 30mbyte/sec bus round several MCUs could be fun, so a CPLD/FPA may make things easier, with minimal HDL effor
You will need one or two SD interfaces.You can write a CF controller in a couple days. If you really get with it, you can have SD 4bit mode written in several days. Done both.
You took me a bit by surprise there. Since I'm not an experienced HDL programmer I wasn't too eager to build the flash memory controller from scratch,
This might be an option
http://www.toshiba-components.com/memory/benand.htmlSLC NAND flash with inbuilt ECC. You still need to manage bad blocks, but that can be pretty easy.
ECC during write isn't all that hard to do - it's just generating parity bits. read is a little more fiddly but you're not so time constrained & you could do that on a host PC after uploading
- I found that bad blocks can be identified by longer erase times, so a simple pre-formatting operation can find all the bad blocks. You can then deal with them by building a simple lookup table of logical address to physical address, e.g. in a seperate SPI flash. As you are streaming data out, you will be needing to do the translation in a very predicatable fashion so this should be easy.
A big advantage of going with discrete NAND flash is you have full control over erase & program times, and when you do them - the problem with a generic disc type device is it doesn't knwo what you are about to do next, so for example it will always erase a block before writing. In your application you will be able to pre-format, and so have zero erase time issues. (Assuming you fill the memory then stop, and not a rolling FIFO buffer)
Your page program times will also be very predictable, so you will be able to have minimal RAM buffering (easily low enough to use FPGA's internal RAM) by interleaving writes between 2 chips, or 2 banks within one chip (i.e. write to one chip during page program time of the other).
I just looked at a random NAND datasheet, which shows typical page write times of 200uS (2K page) and block erase (128) of 500uS.
In terms of ruggedness, not having a device in a socket could be a big improvement.
Raw NAND chips are very easy to interface - the interface is standard - I recommend Microns datasheets as being particularly well written. Certainly easier than any CF or SD type device for your 'write a big single lump of data' type application.
As you only need 2gbytes, I'd say the simplest solution by quite a long way is FPGA and NAND flash chip(s), probably a microcontroller to oversee things like start/stop control & generating the badblock map etc., but wouldn't need to ever see the actual data, so no major speed or memory requirements.
One disadvantage of this is you can't just plug it into a PC to get the data out, but getting fast data out with FTDI's high-speed USB devices is pretty easy if you don't need ultimate performance.