STM32F4 with external simultaneous ADC

[rheb1026]

I was looking to use a simultaneous sampling ADC in my software radio receiver to digitize the I and Q streams and was looking for some guidance. I was looking to use something like the AD7902 which uses two standard SPI blocks - one for each converter. Obviously I can just read from each one individually, but the datasheet shows each of the clock, input, and conversion lines tied together with the two data output lines independent which got me thinking... Is there an easy way to use a single SPI in the STM32, but use a dual input of the two data lines? I looked at the QSPI peripheral, but there doesn't appear to be an obvious way to do this. They only seem to be set up for accessing memory

[langwadt]

I was looking to use a simultaneous sampling ADC in my software radio receiver to digitize the I and Q streams and was looking for some guidance. I was looking to use something like the AD7902 which uses two standard SPI blocks - one for each converter. Obviously I can just read from each one individually, but the datasheet shows each of the clock, input, and conversion lines tied together with the two data output lines independent which got me thinking... Is there an easy way to use a single SPI in the STM32, but use a dual input of the two data lines? I looked at the QSPI peripheral, but there doesn't appear to be an obvious way to do this. They only seem to be set up for accessing memory

why not daisy chain them? (fig.46 in the datasheet)

[rheb1026]

You're right I could do this, and it might end up being the easiest way to go. I guess I was hoping that there would be a way to get the data out of both converters on the CLK stream for only one - reading both 16-bit data registers using only 16 clocks

[Scrts]

I'd use two SPI peripherals with DMA then.

[bobaruni]

Take a look at TI's ADS8363 http://www.ti.com/product/ADS8363, I think you might be able to do it with a single SPI peripheral.
You also have the bonus of built in oversampling (this may or may not be useful on an I/Q SDR) and also a mux on each ADC to let you choose different frequency bands.
I'm about to test an ADS8363 with an STM32F373 (cortex M4F) in the next few days.

[ajb]

I looked at the QSPI peripheral, but there doesn't appear to be an obvious way to do this. They only seem to be set up for accessing memory

I'm just working with the QUADSPI in an STM32F7 and remembered this thread.  You can definitely use the QUADSPI for non-memory applications in "indirect" mode.  Individual transactions are setup in the QUADSPI->CCR register, which defines transaction mode, instruction format (if any), data format (if any), address format (if any), and alternate byte format (if any).  Of course, in a case like yours the data from the two ADCs winds up interleaved and will need to be separated later on, because in all modes the QUADSPI only transfers one stream of data regardless of the number of data lines used.

If the ADCs don't require any instructions to be issued, and you just need to yank the data out of them, the below should be all you need.  Writing to CCR.INSTRUCTION is sufficient to start a transaction in indirect mode if no address is being issued.  If you don't need to issue an address, instruction, or alternate bytes most of CCR can be kept at 0 and you only need to configure the mode and the data format.

Code: [Select]

// initialization
QUADSPI->CR = QUADSPI_CR_FSEL; //if using bank 2, otherwise leave out
uint32_t div = ( AHB_CLK_FREQ / QUADSPI_CLK_FREQ ) - 1;
QSPI->CR = (div << QUADSPI_CR_PRESCALER_gp);

QUADSPI->DCR =     ( 7 << QUADSPI_DCR_CSHT_gp);  // 7 -> 8 clock cycles of nCS high between transactions

QUADSPI->CR |= QUADSPI_CR_EN;


// start a transaction
QUADSPI->DLR = 3;  //number of bytes to receive - 1
QUADSPI->CCR =
QUADSPI_CCR_FMODE_INDREAD |
QUADSPI_CCR_DMODE_DUAL; //data will be received on IO0 and IO1

//wait for transaction to be finished
while( !(QUADSPI->SR & QUADSPI_SR_TCF));
QUADSPI->FCR = QUADSPI_FCR_CTCF; //Transfer Complete flag must be cleared manually

//read data out of 32-byte FIFO via QUADSPI->DR

In indirect mode, DMA treats QUADSPI as a peripheral (versus as memory location in memory mapped mode), and you can trigger DMA transfers based on the QUADSPI FIFO level.  You should be able to use one DMA channel to write to QUADSPI->CR to trigger a read from the ADC and then use a second DMA channel to read out from the FIFO for fully-automatic continuous reads.

Hope that helps.

[rheb1026]

Thanks for the info! I'll definitely look into this!

[danadak]

Or use a PSOC with dual 12 bit SAR and a ton of other stuff (including
DSP engine). See attached.


Regards, Dana.

[rheb1026]

The PSOC is on the list of things I want to learn!

[qmmdzd]

??STM32??ADS8363? 957673760@qq.com

[danadak]

Some additional info -

1) Routability
2) Fast 12 bit SAR A/D and slow 20 bit DelSig
3) DFB (Digital Filter Block) that is dual channel, handle FIR or IIR filters, or DFB
can be used as a GP fast processor block, similar to RISC block
4) MSI logic elements GUI based and/or the UDB Verilog capability. Eg. the FPGA
like capability
5) Onboard Vref
6) IDAC, VDAC, OpAmps (up to 4), comparator, mixer, switch cap, analog mux....
7) LCD,  COM, UART, I2C, I2S, One Wire, SPI, Parallel, LIN, CAN, BLE, USB
9) Custom components capability, create with schematic capture or Verilog
10) DMA to offload processes like filters, COM, Display
11) ARM M0 (PSOC 4) or M3 (PSOC  5LP) or 8051 core(PSOC 3) or M0+/M4 dual core PSOC 6
12) Extensive clock generation capabilities
13) All components supported by extensive prewritten APIs

https://www.element14.com/community/thread/23736/l/100-projects-in-100-days?displayFullThread=true

http://www.cypress.com/documentation/code-examples/psoc-345-code-examples

Great video library

Attached component list.  A component is an on chip HW resource.

Free GUI design tool with schematic capture, "Creator". Components have rich API library attached
to each component. Compilers free as well.

PSOC 4 is low end of family, consider 5LP parts as well. PSOC 4 also has arduino footprint boards (pioneer) as well. PSOC 6 dual core M0+/M4.

https://www.elektormagazine.com/labs/robot-build-with-cypress-psoc

http://www.cypress.com/products/32-bit-arm-cortex-m-psoc



https://brightcove.hs.llnwd.net/e1/uds/pd/1362235890001/1362235890001_5241352463001_2606504288001.mp4?pubId=1362235890001&videoId=2606504288001



Regards, Dana.