FTDI FT232H in Synchronous FIFO questions.

[Boscoe]

So this will be the first time I integrate an FTDI USB transceiver in one of my projects. I'm going to be using the FT232H in synchronous FIFO to send a large amount of data from an image sensor via an FPGA. I have read the datasheet but I just need a few clarifications on the system before I write any Verilog or C++.

Basically I'm unsure how the FIFO aspect works. I think there is not hardware FIFO. The way I see it the FPGA will clock data into the FT232H then it [FT232H] will send the data over USB and then the data is absorbed by the D2XX driver ready to be read by the application I have written.

I wonder if someone with some experience of this could give me a few pointers.

Thanks

FT232H datasheet: http://www.ftdichip.com/Support/Documents/AppNotes/AN_165_Establishing_Synchronous_245_FIFO_Communications_using_a_Morph-IC-II.pdf

D2XX programmers guide: http://www.ftdichip.com/Support/Documents/ProgramGuides/D2XX_Programmer's_Guide(FT_000071).pdf

[electro-logic]

Hello,

I've written some articles about FPGA and FT232H: http://electro-logic.blogspot.it/2014/03/fpga-comunicazione-ad-alta-velocita_3163.html

Just use Google Translate 

You can also add another FIFO on FPGA side to buffer image sensor's data
Leonardo

[tmbinc]

We've used sync FIFO mode on OpenVizsla. (Now, make fun of OpenVizsla all you want, but _that_ part really worked well.)

On http://debugmo.de/2014/08/ov3-fpga-design/, click on FT2232H on the very left, and a description (and diagram) will appear below the block diagram. (Sorry, I'm not a web programmer)

(Does this forum support WaveDrom timing diagrams somehow? That would be useful.)

https://github.com/openvizsla/ov_ftdi/blob/master/software/fpga/ov3/ovhw/ftdi_bus.py is some migen code, but I admit it can be confusing if you're not used to migen.

It's called FIFO mode because it acts like a hardware fifo - you put data on the bus, and clock cycle where WR# and TXE# are both asserted, that data enters the "FIFO" (and appears on the host).

[daveatol]

I had a play with the FT232H and an FPGA back in 2011 as my first VHD/FPGA attempt. I could maintain 30MB/s write and 38MB/s read rates. The FT device cannot accept continuous data however, on a periodic basis. This means you have to be able to buffer around 6us of data every 125us (that's the USB high-speed microframe period). You can see this if you tie the WR# low and monitor the TXE# line (see attached figure).

The VHDL for the interface to the FT232H is extremely simple. I can provide it if you want.

Figure 1 TXE# for 30/15/7.5MBps Continuous Sampling (#ATTACHED#)

[marcan]

I managed 42MB/s device->host at one point with the FT2232H, under Linux with a USB3 (xHCI) host. 40MB/s with a USB EHCI host and 38MB/s with an older kernel, so clearly newer drivers and newer hardware help get more throughput out of USB2.0.

The device does have a hardware FIFO, but the interface also looks like a FIFO. It's very similar to the kind of interface that you'd expect from a normal producer/consumer block RAM FIFO module in an FPGA, except for the bit where tx and rx both share the same bus so there's arbitration involved. Whenever I work with the 2232H I usually throw my own FIFOs in on the FPGA side though, unless whatever you're interfacing already allows pauses in data consumption.

The easiest way to look at is is as a chain of FIFOs. The FTDI chip has its own FIFO. You will probably implement a FIFO in your FPGA. The FTDI will accept data over its synchronous interface from your FIFO, as long as its own FIFO has space. The host has its own buffers (as part of the URBs/buffer descriptors maintained by the USB driver). It will poll the FTDI chip (via IN packets) if there are free/empty buffers in the queue. The FTDI will reply to one of those packets once it has a full USB packet's worth of data (512 bytes for bulk) or after a timeout if there is less data available (the FTDI datasheet has some documentation around this, but you can mostly ignore it unless your application is very latency-sensitive; the data will get to the host eventually).

Keep in mind that the FTDI chip is the clock master of the interface, so you can either run your FPGA core clock off of the FTDI's 60MHz interface clock, to avoid having to cross clock domains, or you can use a clock-domain crossing FIFO in the design and run your core clock off of whatever oscillator you want.

[marshallh]

It's dead simple. Just stuff the bytes in, they go into a magical buffer (actually the chain of device ram > polled usb frame > device driver buffer), and you send a FT_Read() on the PC to get the data.
In synchronous mode, run the FT232H's clock out into your FPGA's clock inputs so that you can run the usb junk in its own clock domain. I use a dual ported bram this way.
Sure beats doing USB yourself (trust me)

I found some errata while using Asynch mode. Had to pad out timings a few cycles longer than the datasheet specified. FTDI have a history of device errata, just keep in mind while working.

[Boscoe]

Thank you everyone for the replies, they have clarified a few things.

[zhihuihou]

Recently , I'm developing upon the chip FT232H, but I get some problems when the pc application read amount of data from the usb. sometimes, the read data will be lost some random bytes, I don't know what happened, can you tell me why and supply your VHDL code to me? my email address is hzh5480248@163.com