STM32H7 ADC characteristics

[hk.ketabdar@gmail.com]

Hi,

I'm working on a setup with a filter and some electronics to get an analog signal ready for a ST microcontroller (STM32H723VG). I want to simulate everything, even the part inside the microcontroller that handles the signal. But the problem is, I can't find the info I need in the microcontroller's manual. The manual does have a table that shows how long it takes to sample different signals, depending on how much resistance the source has. But I'm not sure how to use this info to figure out the resistance and capacitance inside the microcontroller.
So far, I've tried to guess the resistance and capacitance by looking at the sampling times in the table. I came up with a guess of 1K ohm for the resistance and 8.5 pF for the capacitance. But I'm not sure if 1 kilo-ohm is right. I want to sample at about 4MSPS, but 1 kilo-ohm might be too much resistance to do that quickly enough within 0.5LSB and with the required sampling time of 60-70 nanoseconds.

Here are some details about the setup:

Microcontroller: STM32H723VG
ADC input range: 0-3.3V
Signal Bandwidth: 1MHz (-3db)
Filter attenuation at 4MHz: -40db
ADC Resolution: 12 bits
ADC channel type: Fast Channel
ADC Clock: 40MHz
Sampling time (2.5): 62ns
Sampling frequency in dual mode: 8MSPS (two ADC at 4MSPS)

Note: The images show the last stage for level shifting, charge bucket and ADC internal

Any help or advice would be great.

Thanks!

[mtwieg]

Datasheet says that the sample and hold capacitor Cadc is 4pF in 16b mode, 5pF in 12b mode. Seems to be missing values for the mux resistance Radc.

But generally they provide recommended external component values in order to help users get specified performance without doing a ton of analysis. Typically when I want to use the ADCs of an MCU I follow their guidelines (either according to their documentation or reference designs they're provided).

But in your case if you're going for such high sampling rates, it's unclear what sort of performance you should expect, even with their recommended component selection. The datasheet only specifies one value of SNR/ENOB for each ADC type, without providing what conditions it was measured under. But another table implies that effective resolution (and thus SNR) can be traded with sampling rate. Not very helpful, but that's not surprising for a part like this.

If you really are concerned about this, I would get a dev board and measure real performance. There's a lot more going on than a simple sample and hold circuit...

[nimish]

Datasheet says that the sample and hold capacitor Cadc is 4pF in 16b mode, 5pF in 12b mode. Seems to be missing values for the mux resistance Radc.

But generally they provide recommended external component values in order to help users get specified performance without doing a ton of analysis. Typically when I want to use the ADCs of an MCU I follow their guidelines (either according to their documentation or reference designs they're provided).

But in your case if you're going for such high sampling rates, it's unclear what sort of performance you should expect, even with their recommended component selection. The datasheet only specifies one value of SNR/ENOB for each ADC type, without providing what conditions it was measured under. But another table implies that effective resolution (and thus SNR) can be traded with sampling rate. Not very helpful, but that's not surprising for a part like this.

If you really are concerned about this, I would get a dev board and measure real performance. There's a lot more going on than a simple sample and hold circuit...

Read AN5354

In short: you need to be using a specific BGA package that exposes direct-to-adc channels, have an external 3.3Vref and be sampling a full-swing (6.6V) differential signal for the ADC to get datasheet numbers. You'll also want to have a 50MHz/25MHz low noise external crystal or clock source. Then you can actually get close to the ENOB/sample rate.