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GCC compiler optimisation

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One very crooked company made usb hardware buffers with holes (like cheese). Real 16bit data, 16bit empty, 16bit data, 16bit empty, and so on. To transfer data, the company wrote a simple code that GCC optimized to 32bit reads. GCC knows that the buffer is always clear before starting work, and therefore performs the addition with a shift (it is more convenient for it).
You can look for a data transfer error indefinitely when you accidentally deleted a buffer flush.
So, DMA can read sparse data, and write without emptiness. Able to do in the opposite direction (creates cheese). But the configurator from the company prohibits such DMA settings.


--- Quote from: peter-h on May 27, 2023, 06:00:57 pm ---If I was writing code which actually needs the speed I would do an asm function for it.

--- End quote ---

It's safer.

Other than needing 3 or 4 or 5 different asm versions if the code is going to be widely used. Always keep a plain C (with idioms you hope will be recognised) as fallback when the code is compiled for an ISA you don't expect.

A compiler that optimizes a byteswap of memory into a load (at memory speed - 10s of nanoseconds) followed by a SWAP instruction (sub-nanosecond speed, once the value is in a register) can handle arbitrary network traffic in any endianness with essentially no performance penalties.  Allowing Intel and AMD to sell into significant markets that used to be dominated by MIPS CPUs (which could be configured for different endianness.)
As of a dozen year ago, that's making switching decisions (in software) for over 4 million packets/s.


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