EEVblog® Electronics Community Forum
Electronics => Microcontrollers => Topic started by: XaviPacheco on September 24, 2018, 03:28:35 pm
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I've attached a fragment of the Nucleo L432 clock tree. At first insight I thought that Timer 2 (connected to APB2) were clocked at "APB2 Timer Clocks" frequency. But then I realized that I was wrong, and that timers peripheral are clocked at "APBx Peripheral Clocks" (makes sense). So, what's the purpose of APB2 Timer clocks?
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Most STM32 devices seem to have this interesting concept of a seperate timer kernel clock that has an optional doubler, which is automatically enabled when you enable an upstream divider.
The reference manual explains this in detail. The idea is, say your HCLK (AHB clock) is 80MHz, and you want to divide it by 2 to make your 40MHz PCLK2 (APB2 clock). Now, the timer will have separate interface clock, and the kernel clock which runs the counter - the kernel clock is derived by doubling the 40MHz clock, so the timer runs at 80MHz again.
This doubler is automatically enabled and disabled based on the PCLK2 divider. The idea is, while the interface freq is limited, the timer can run higher, so they do this.
For example, you might want to save power with lower interface clock. Now, you can change the bus prescaler on the fly, and the timer will still run at the same frequency (by switching the doubler in or out).
Do check the details from the reference manual. For example, what is the basis of the x2 multiplier being enabled or not. It may be something else.
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I've attached a fragment of the Nucleo L432 clock tree. At first insight I thought that Timer 2 (connected to APB2) were clocked at "APB2 Timer Clocks" frequency. But then I realized that I was wrong, and that timers peripheral are clocked at "APBx Peripheral Clocks" (makes sense). So, what's the purpose of APB2 Timer clocks?
What Siwastaja said, plus:
APBx is just a generic name for APB1 or APB2, used (sparingly) in the manuals when the description applies to both, or a register has two similar instances, one for each APB.
A timer peripheral will be driven by either APB1 or APB2.
But you are actually right, you were in fact wrong as TIM2 is connected to APB1 according to Figure 1 in the datasheet (https://www.st.com/resource/en/datasheet/stm32l432kb.pdf)
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But you are actually right, you were in fact wrong as TIM2 is connected to APB1 according to Figure 1 in the datasheet (https://www.st.com/resource/en/datasheet/stm32l432kb.pdf)
:palm:
As I'm using TIM1 and TIM2 and they are connected to APB2 and APB1 respectively I confused myself when writing this post. At the end of the day my confusion was between APBx Peripheral Clocks and APBx Timer Clocks in CubeMx Clock Tree.