Author Topic: Generate DVI-D Dual-Link signal with FPGA?  (Read 777 times)

0 Members and 1 Guest are viewing this topic.

Offline davorin

  • Supporter
  • ****
  • Posts: 809
  • Country: ch
Generate DVI-D Dual-Link signal with FPGA?
« on: April 26, 2018, 09:55:30 pm »
EHLO (o;

As it is easy possible to generate 1080p60 TMDS signals I looked around for the DVI-D dual link timing specs if it is feasible to generate 2560x1440 with 6 TMDS channels with FPGA...

According some text I found the pixel rate is around 240MHz compared to 165MHz at 1080p.

I thought that DVI-D dual link can use the same pixel clock but spreads odd/even pixels across each bundle of 3 TMDS links?

 

Online hamster_nz

  • Super Contributor
  • ***
  • Posts: 1933
  • Country: nz
Re: Generate DVI-D Dual-Link signal with FPGA?
« Reply #1 on: April 27, 2018, 05:11:17 am »
Yes it is possible.

I thought that each link controlled half the screen (left and right), but might be mistaken. Look for the Digital Display Working Group (DDWG) documents on the web to be sure.
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Online hamster_nz

  • Super Contributor
  • ***
  • Posts: 1933
  • Country: nz
Re: Generate DVI-D Dual-Link signal with FPGA?
« Reply #2 on: April 27, 2018, 06:57:38 am »
Yes it is possible.

I thought that each link controlled half the screen (left and right), but might be mistaken. Look for the Digital Display Working Group (DDWG) documents on the web to be sure.

I was wrong the pixels are interleaved - have a look at "Channel Mapping" on page 26 of http://www.cs.unc.edu/~stc/FAQs/Video/dvi_spec-V1_0.pdf
Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline davorin

  • Supporter
  • ****
  • Posts: 809
  • Country: ch
Re: Generate DVI-D Dual-Link signal with FPGA?
« Reply #3 on: April 27, 2018, 07:33:54 am »
Thanks Mike for tbe pointer :-)

Seems you are the Guru everything FPGA display related ;-)

Do you know anything regarding eDP displays with lower resolution (< 1920x1080) ?
Do they always require a GTP or would be a OSERDES enough with an Artix 7 as the pixel rate is around 1.5Gbits/secs?

BTW: I am almost through converting your brilliant hdmi processing design to verilog, which will be the basic for my hdmi2rgb matrix panel project, though currently limited to 192x128 resolution ;-)
 

Online hamster_nz

  • Super Contributor
  • ***
  • Posts: 1933
  • Country: nz
Re: Generate DVI-D Dual-Link signal with FPGA?
« Reply #4 on: April 27, 2018, 08:45:25 am »
I don't know if eDP allows a lower speed option, but DisplayPort uses fixed data rates, and then only uses the data slots it needs to send pixels. Even 640x800 is sent using a high speed link.

The rates are fixed at 1.62Gb/s, 2.7Gb/s and 5.4Gb/s - all outside of the rates achievable with standard SERDES pins, even if they were electrically compatible.

Unlike HDMI, because it uses Clock Data Recovery I expect you will not be able to establish a valid link if you try to stray more than a few % from these speeds - the receiver's PLL will not be able to lock successfully.



Gaze not into the abyss, lest you become recognized as an abyss domain expert, and they expect you keep gazing into the damn thing.
 

Offline asmi

  • Frequent Contributor
  • **
  • Posts: 668
  • Country: ca
Re: Generate DVI-D Dual-Link signal with FPGA?
« Reply #5 on: April 27, 2018, 10:57:41 am »
Do you know anything regarding eDP displays with lower resolution (< 1920x1080) ?
Do they always require a GTP or would be a OSERDES enough with an Artix 7 as the pixel rate is around 1.5Gbits/secs?
MGTs are required for DP. You can also implement HDMI 2.0 with MGTs using retimer SN65DP159 (I saw this idea in the schematic of ZCU104 devboard).
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf