Author Topic: Getting started with FPGAs: choices on HDL and devboards  (Read 19883 times)

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Offline ivan747

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Getting started with FPGAs: choices on HDL and devboards
« on: May 06, 2013, 10:20:13 pm »
I want to spend my last school summer break wisely by learning how to program FPGAs. Now, I have a couple of questions. As anyone getting started I am overwhelmed by terms I don't know so I can't do an informed choice. These questions have been asked hundreds of times when it comes to MCUs, but what about FPGAs:

  • Which hardware description language is best to get started? (notice I don't ask which one's the best because that's very subjective and probably dependent on the application)
  • Which method is best to learn? By this I mean, should I go for something analogous to an Arduino/Launchpad, simulators, actual hardware on a SMD breaktout or expensive development boards with integrated peripherals?

I can order online and I prefer a budget of $30 but I can extend it up to $100. I would also like to have a varied stock of chips in the future, as I currently do with microcontrollers, but that comes later.

For $30 I can't really get much, but you know, since we have RasPi for $40 and MSP430 for $4.30 I thought it is possible. After this a fake programmer will probably cost me $50, but that is easy to justify after I learn on something like the board I hope to get.

I learned MCUs by purchasing a simple 8 pin PICAXE. It's essentially a PIC with a bootloader that allows you to download BASIC code to it. It has a built-in interpreter.  Then I moved to PIC by buying a JDM programmer and programming in C. So I didn't start out with anything fancy, but FPGAs are not that simple either.

Thanks for all.
-Ivan
 

Offline free_electron

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #1 on: May 06, 2013, 11:25:05 pm »
get a terasic board. for 50$ you have the device + the programmer.

as for the easiest language to start ... systemverilog or verilog 2005.

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Offline mikeselectricstuff

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #2 on: May 06, 2013, 11:46:27 pm »
The Lattice LCMXO2-7000HE-B-EVN board is in your budget and has onboard programmer. No peripherals though.

I would very strongly recommend you define a specific thing to develop an work towards that, instead of random tinkering. This forces you to work through issues instead of wandering away onto something else

I only know VHDL , but from what I hear, VHDL is less likely to land a beginner in trouble as it has more thorough type checking

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Offline MacAttak

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #3 on: May 07, 2013, 12:03:34 am »
I am just getting started in it, I always assumed that it would be just a bit too difficult of a learning curve for me at this point. I ended up getting a Mojo board (decent Spartan-6 chip) from Embedded Micro, and have been very happy with it. Cost is $75 and no external programmer is needed. It is a very minimal board - just the FPGA, power jack, micro USB port for programming (using an AVR chip on-board), reset button and 7 LED's. All of the signals (including almost 200 IO pins) are broken out into 1mm headers.

I don't get the impression that language choice really matters all that much for most things. I went through the Xilinx ISE tutorial material and everything was shown in both Verilog and VHDL and it really wasn't very different.
 

Offline nctnico

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #4 on: May 07, 2013, 12:09:44 am »
I don't know if a larger project is a good idea. The first thing I ever made on a CPLD was a counter.
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Offline chickenHeadKnob

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #5 on: May 07, 2013, 12:12:05 am »
I am in a similar situation to Ivan and was about to buy a Papilo pro from Gadget Factoryhttp://papilio.cc/index.php?n=Papilio.PapilioPro Spartan LX6 with 64 Mb SDRAM. What do the experienced folks think?
 

Offline mikeselectricstuff

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #6 on: May 07, 2013, 12:20:22 am »
I don't know if a larger project is a good idea. The first thing I ever made on a CPLD was a counter.
Start small, and build gradually into something more substantial, but it really helps to have an end goal.
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Offline marshallh

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #7 on: May 07, 2013, 12:53:00 am »
I am in a similar situation to Ivan and was about to buy a Papilo pro from Gadget Factoryhttp://papilio.cc/index.php?n=Papilio.PapilioPro Spartan LX6 with 64 Mb SDRAM. What do the experienced folks think?

Get the DE0-Nano instead. It has an Altera Cyclone IV.
Avoid the Xilinx tools like the plague (yes even they know ISE is crap).
Don't be another one that ignores my advice then bawws at how hard fpgas are unnecessarily :)
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Offline ivan747

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #8 on: May 07, 2013, 01:24:20 am »
get a terasic board. for 50$ you have the device + the programmer.

This DE0-nano is actually $80 but the built-in peripherals aren't too bad. It's got RAM, EEPROM, basic LEDs and switches, ADCs and even an accelerometer.


Now, LCMXO2-7000HE-B-EVN (what's going on with these model numbers?).

The price seems very atractive, built-in RAM too. Seems like this is more what I need. On the DE0-nano I have things I probably won't use, like the accelerometer or the 32MB of RAM. I am not a crazy programmer, at least in programming languages. Who knows, maybe I will become a HDL freak.

The DE0-nano features a much more powerful chip but I can't find a use for it right now. Also, the Lattice chip has hardwired peripherals I can use, like I2C. The DE0-nano's series of chips can even support PCI Express! I like it, but I will keep it for when I can take advantage of the student discount.

So far the LCMXO2-7000HE-B-EVN is the chosen one.


I would very strongly recommend you define a specific thing to develop an work towards that, instead of random tinkering. This forces you to work through issues instead of wandering away onto something else

As a project, I want to do a "lab-grade" chronometer/timer with external triggering and such. It could accept 10MHz input, provide a 10MHz and 1pps outputs. It can also have a real-time clock and store datestamps and what not. But it will start as a chronometer with external trigger. I know there must be some variation of the frequency counter that does this but whatever, I need an excuse to work on FPGAs. You can do this all with discrete components, of course, but again, I need an excuse to work with FPGAs. And I suspect the board will be smaller if I use an FPGA instead of discrete logic. I want to make it small.

I am just getting started in it, I always assumed that it would be just a bit too difficult of a learning curve for me at this point. I ended up getting a Mojo board (decent Spartan-6 chip) from Embedded Micro, and have been very happy with it. Cost is $75 and no external programmer is needed. It is a very minimal board - just the FPGA, power jack, micro USB port for programming (using an AVR chip on-board), reset button and 7 LED's. All of the signals (including almost 200 IO pins) are broken out into 1mm headers.

I don't get the impression that language choice really matters all that much for most things. I went through the Xilinx ISE tutorial material and everything was shown in both Verilog and VHDL and it really wasn't very different.

Mojo is still on pre-orders  ???

I am getting the same impression on the language as well. Are they interchangeable? i.e. do manufacturers support both languages extensively?
 

Offline free_electron

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #9 on: May 07, 2013, 03:25:15 am »
The language is irrelevant. the tools handle both equally fine.
Verilog is easier to 'step-in'
- there is less keyboard pounding involved
- it's more productive  ( not my words. year after year it is proven again in 'coding contests' between vhdl and verilog guru's . they get 30 minutes to desing something. the veriloggers are alway fully ready, fully debugged and the vhdl'ers are still fixing punctuation and lexical errors in their source )

Now, irrepective of the language used, the mindset is TOTALLY different from working on a CPU. A CPU works sequential. in FPG aeverything happens simultaneously under control of a clock. the 'program' in the fpga determines what is ALLOWED to happen. ( on a cpu it's more 'what must happen')

an important stepstone in beginning work with synthesis languages ( whetehr in cpld  /fpga or ASIC work ) is UNDERSTANDING the synthesis process.
This is where 99% of the people beginning this stuff go catastrophically wrong. there are very few books that explain this process and the basic concept is lost. this leads to ugly ,kludged code, that often has uncovered scenarios and doesn't exactly do what you expect it would do. you then need to patch in more 'conditions' to cover these holes. if you understand the synthesizer you won't run into these problems.

The languages have evolved use the latest versions as they solve annoyances that often get frustrating very quickly.

Verilog2005 (sometimes called SystemVerilog although they are not 100% the same) is now the de-facto verilog standard. VHDL sits at release 204 i believe and 2010 is almost (very lately) finished but only some hi end tools support that one .

How does a logic synthesizer work ?
it essentially needs to translate a list of instructions and conditions ( if/then/else , mthematical and boolean operations etc ) into a block of logic. the way we describe theis block is essentially 'sequential'. it is a bunch of lines of code , each line containing some instructions. so the synthesizer reads these line by line and builds code.. but this s contradictory to the concept of digital logic ! everything has to happen at once. so how do we translate this 'list' into parallel form ?

the solution is simple :
we begin at the INPUTS, read the first line  and build a little cloud that connects inputs to what is required by the line of code.
the next line of code as 'glued on' at the end of the previous build step.
once we hit the last line of code we have reached the OUTPUTS of the block. at every step the synthesizer can cut wires going to outputs and 'inject' a new block. it can also splice existing signals.

so we grow our logic from INPUT to OUTPUT.

an example ( in pseudo laguage so it is easy to read)

if x = 1 then
 z = a and b
else
 z = a or b
end if

so this describes a block that can switch between an and and an or operation under control of a signal.

so the synthesizer will begin building :

if x=1 then  : take input pin'X' and drive a mulitplexer 'select' signal ( if/then/else constructs are built using multiplexers).
z = a and b  : output of the multiplexer goes to 'Z' . Apply signals A and B to an AND gate. Ouput of the ANd gate goes to the multiplexer input for
'X=1'
else : this is the other multiplex case
z = a or b : take a and b and attach to an or gate. output of the or gate goes to mulitplexer input for 'x=0'

A mulitplexer is a simple boolean equation. a mulitplexer has a control line (S) , two inputs (x and y) and an ouput (z). the equation is  Z = (X.Sn) + (Y.S)

since our code generates more boolean stuff we can now substitute terms into a massive equation, squash it, reduce it and done. we have logic.

when code becomes more complex you will need more constructs

if (enable=1) then
  if updown =1 then
    count = count +1
  else
   count = count -1
  end if
else
 if reset = 1 then
    count = 0
 else
   if preset = 1 then
   count = inputvalue
 end if
end if

there. the bove code is a simple counter that can count up and down, has a reset and a perest input. reset makes count zero , preset loads an input value. but.. can you figure out what will happen in the following cases :

i make reset high and i make preset high ... (this one is fairly obvious)
i make reset low and preset low ... (this one is  bit harder.. it is actually undefined as there is no full definition for this pathway...

this can lead to very strange situations and logic not doing what you expect it to do . and this is a common pitfall. your block of logic does not work right under all possible conditions because you forgot a pathway ... you need to go over the entire tree and figure out hat happens when... reading a large block becomes tedious to understand.

if you use the scheduling technique this problem will not occur.
Scheduled code is code written in such a way that there are no ambiguous or forgotten conditions possible by using the synthesis mechanism.
both VHDL and Verilog have a clause in the language definition that states the following : Logic shall be implemented in the ORDER it was WRITTEN.

what does this mean ? this goes back to the way the synthesizer builds logic. it read a line , builds a little cloud of logic , splices input sgnals and cuts the prior generated output to inject the new block inbetween.

so, the LAST line of code in a block sits CLOSER to the output than the first line of code.

using this mechnism we can rewrite our counter as follows :

if updown =1 then
   count = count +1
else
  count = count -1
end if
if enable =0 then count = count
if reset =1 then count = 0
if preset =1 then count = input value


the lowest line in this list has the HIGHEST priority. we don't care what has happened earlier. as the lowest line sits closest to the output it takes control

so , depending on 'updown' we count up or down.
if enable is zero then count remains count. this line sits closer to the output. so it doesntmatter what updown just wanted to do. if this line is active then count will not move !
if reset =1 thencount = 0. i dont care that enable wanted me to stay where i was.. theis line says : if reset is low : counter becomes zero. screw what happened before !
and lastly if preset is 1 then i load the input value.

there are no hidden pathways. something will happen , no matter what. the priorirty of 'what' happens is purely defined by the order of the instructions.

if someone tells you reset needs priority over preset you simply swap those two lines.

for simple things this may not be that obvious but if you start writing large complex blocks this way of coding saves a lot of time and it eliminates problems

for example an i/o block that talks to a bidirectional bus that needs tri-stating.

output = Z  ( high impedant)
if (write) then
  case (address)
   0: output = somevalue
   1: output = someothervalue
   9 : output = anothervalue
   default : output = 0xdeadbeef
end if


there we go. by default the 'output' pin is high impedant. only if 'write' is logic high will i apply some code that looks at an address and switches through some data.

if they now tell me i need a few  additional modes : in reset all outpus need to be low ,and in writetest mode a special pattern (010101010) needs to be there

i simply add two lines at the end

output = Z  ( high impedant)
if (write) then
  case (address)
   0: output = somevalue
   1: output = someothervalue
   9 : output = anothervalue
   default : output = 0xdeadbeef
end if
if testmode then output = &b01010101
if reset then output = 0


done. this reads very easily . there is no mishmas of if then else elseif and other curly wurly bits.

output is high impedant, except if write is active then we look at address and throw some stuff on there, except if testmode is active then we throw 1010101 on there ,except if reset is active then we throw all zeros on there.

no hidden pathways, no surprizes. very aesy to read and understand , very easy to modify ( priority changes is a matter of moving some lines up or down ) and there is a very good chance it will work first time as you intended it to work.
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Offline marshallh

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #10 on: May 07, 2013, 03:32:04 am »
Have a look at my verilog tips

http://retroactive.be/verilog_tips.pdf

State machines, counters, muxes are the bread and butter of synchronous logic. It took me over a year of head banging (not the good kind) to figure out how to start thinking in the right mindset

I use/abuse the priority ordering that free_electron was talking about all the time. But you need to be very careful as in larger modules you can forget about it and chase bugs for days. I usually put some sort of cycle counter increment at the top and handle resetting inside the FSM cases below, and synch reset FSM resets go at the very bottom
« Last Edit: May 07, 2013, 03:34:04 am by marshallh »
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Online TerminalJack505

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #11 on: May 07, 2013, 08:28:57 am »
I'd recommend getting a bare-bones FPGA board.  If you get a board with a bunch of stuff on it then you'll likely find that all that stuff just gets in the way and wastes I/O pins and power when you want to put your own code on the FPGA. 

I would get an all-in-one type of board only if you have lessons or a book that walk through projects using that particular board.

If you're just starting then, like others have said, you might consider starting with a CPLD.  You can't fit a lot of code on them but you'll want to start small anyway.  If you make your own boards at home then you can buy just the CPLD and make your own development board since a lot of the CPLDs come in hobbyist-friendly packages.

Finally, if you haven't taken formal lessons on digital systems design then I recommend you grab a cheap used textbook on the subject and watch these video lectures. 

To effectively define hardware with an HDL you need to have an understanding of discrete digital electronics and these lectures will give you a good foundation on the subject.  This is very important if you are coming from a programming background!  Verilog and VHDL are not programming languages.  They are hardware definition languages.  You are building a digital system with a textual representation.  You are not programming a CPU.

Random Rant:

If you come from a programming background, you will absolutely hate Verilog and VHDL.  You can tell they were developed by EEs and not software developers.  For example, neither language uses curly braces to denote blocks of code.  Because of this you get code that becomes unreadable when you mix poor indentation habits with just a few levels of nesting.
 

Offline chickenHeadKnob

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #12 on: May 07, 2013, 10:05:03 am »
Thanks to free_electron, Marshallh for pointers, Respect!

I just did the findchips  thing for the altera thats on the DE0 nano: $66.00 for a 256 pin BGA package. The Xilinx on the Papilo pro: $15.50 for a 144 pin lqfp. I can't tell how much this is apples to oranges as I don't have a good feel as to how to compare them. Superficially the xilinx looks friendlier If I was to develop my own homebuilt boards so the waters just got muddier.
 

Offline nctnico

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #13 on: May 07, 2013, 01:18:38 pm »
when code becomes more complex you will need more constructs

if (enable=1) then
  if updown =1 then
    count = count +1
  else
   count = count -1
  end if
else
 if reset = 1 then
    count = 0
 else
   if preset = 1 then
   count = inputvalue
 end if
end if

there. the bove code is a simple counter that can count up and down, has a reset and a perest input. reset makes count zero , preset loads an input value. but.. can you figure out what will happen in the following cases :

i make reset high and i make preset high ... (this one is fairly obvious)
i make reset low and preset low ... (this one is  bit harder.. it is actually undefined as there is no full definition for this pathway...
IMHO this code should work fine.  An uncovered path (enable, reset and preset low) causes no change. Exactly as the code describes. You showed the scheduling before but I really don't like it because the code doesn't describe what has priority. You have to assume people know about some obscure rule if you allow them to maintain the code. All in all I'm not convinced the problem you outline actually exists. Maybe at some point you made an error in your code which could have been fixed by using a different construct but instead someone showed you an obscure quick fix. At some point if-then-else constructs based on several signals become messy. A better solution is to concatenate the control signals in a new signal (vector) which resembles states and use a switch statement. If you want to play nice you can create a named type with names like LOAD, COUNT_UP, COUNT_DOWN, RESET, etc. Not necessary for this example but for more complex situations definitely something to consider.
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Offline mikeselectricstuff

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #14 on: May 07, 2013, 01:29:39 pm »
I'd recommend getting a bare-bones FPGA board.  If you get a board with a bunch of stuff on it then you'll likely find that all that stuff just gets in the way and wastes I/O pins and power when you want to put your own code on the FPGA. 
..and with cheap, simple boards, it's much less of a deal if the smoke comes out, or if you want to do some solder kludging
Quote
If you come from a programming background, you will absolutely hate Verilog and VHDL.  You can tell they were developed by EEs and not software developers.  For example, neither language uses curly braces to denote blocks of code.  Because of this you get code that becomes unreadable when you mix poor indentation habits with just a few levels of nesting.
My pet hate is  the lack of #define, #include and block comments, and enforced seperation of things like device type and constrints from the HDL source.
These things don't matter much if you're designing an ASIC, but for FPGA development it is highly likely you will have a differnt device on a protoype than a production unit, and there is much more need to deal nicely with product variants, and teh inability to specify these options elegantly with a few #defines is a major PITA
..and why do we need yet another symbol for comments - I'm frequently flipping between VHDL, C and VB on one project - all with their own different comment characters
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Offline free_electron

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #15 on: May 07, 2013, 02:47:25 pm »
@nctnoco: scheduling is not 'obscure'. It is the basic fundament of how synthesizers work ! Both the vhdl and verilog definitions (the ieee specs) have a whole chapter on it. In fact, you cannot pas the 'compiler test' if you do it differently. It is MANDATED by the spec to work that way. So any synthesizer has it.

Scheduling makes the construction of very complex thing very simple with minimal keyboard pounding.  Maintenance is also simple. You never need to wonder in which branch if the ifthenelse soup things go wrong. Just move the line up or down to change priority. Lowest prioirity is at the top. Highest at the bottom.

@mikes electricalstuff : whaddayamean no define ?

'Define something 16'd123
'Define nextstate state<=state+1
'Define resetmachine state<=0
'Define return state <= savedstate
'Define gosub savedstate <= state + 1; state <=

If x =='something ....

Select case state
0: if start then 'nextstate
1: begin
      x <= something
      Nextstate
      If abort then resetmachine
End
2: begin
   'Gosub 1000;
   End;
3: blabla ...


1000: begin
         If |x then
            x<= x-1;
         Else
         'Return;


My statemachines have gosub-return and goto's !
I can even build stacks and make nested constructs.

I use this all the time for serial prototcols. For example a 32 bit packet contains 7 leading zeroes , a sync bit and then, dpeneding on the sync bit either an 8 bit or a 16 bit right aligned payload.
Imstead of mucking about building counters at every phase i have a generic 'downcounter' state. I load the downcounter and 'gosub'. At this point the returnstate is stored , the count begins and the machine returns all by itself. The define construct allows you to define anything. Numbers , code, even multiple lines of code. Note that you need to use the 'backtick , not the regular tick . Its the tick on the topleft keyboard button, paired with the tilde.

Includes exist as well

Same for comment and block comment

// is comment
/* blabl */ is blcok comment.

No different than c.

Oh . I now only noticed you are talking about that 'Very Hard Design Language' do yourself a favor and switch. There are good verilog code editors with auto indentation, code collapsing and more. ( they exist for vhdl also)

My main gripe with vhdl is that there is too much typing involved ( keyboard pounding) and duplication of work. You need to define all signals twice.
If x is an output you cannot write x=x+1 as you cannot read back... You need to define an intermediate signal to bring the output back in. Then there is the muckery with all the libraries. Std-blabla ieee-blabla. There is maths , boolean and you need to provide the marshalling between them. Synopsis has its ow libraries that are not compatible with ieee and it all becomes soup...
And in every block of code you need to reload the libraries. How stupid is that ?

This misery stems from the original project. HDL was a darpa project to make a uniform language to describe hardware. This can be anything. From a nut or bolt , a wing of an aircraft , a chair .. Anything.  See it as a kind of xml precursor. The HDL in itself has no concept of anything. It is just a storage and retrieval format for information. You can extend the language using libraries. You can define what is a zero and a one and a tristate and a dont care. You can define what the + operator does for numbers, for strings, or for wakalixes (wakalixes being something you invented. If you need to add two wakalixes togethere here is how you do it. Basically operator overloading.

So, some other darpa project Vhsic : very high speed integrated circuit. Was looking for a way to describe circuitry in textual form and do away with schematics. Vhsic and hdl met each other , the libraries were written and off we go. Vhdl was born.

But it fits like pliers on a pig ! It is a constraintfile, and a set of libraries bolted on to a generic language processor.

Verilog was written fro. The beginning to describe logic. So it doesn't need all the curly-wurly bits.

Both languages produce exactly the same output and are equals.
Vhdl is just the grumpy sauerkraut snorting german while verilog is a friendly british grandma 'care for a crumpet and some tea ? '

You pick what you want to deal with every day .. The saur kraut , or tea and crumpets.
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Offline krivx

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #16 on: May 07, 2013, 03:35:49 pm »
The Lattice LCMXO2-7000HE-B-EVN board is in your budget and has onboard programmer. No peripherals though.

Is there a source for these apart from Digikey? Rs and Farnell both stock similar looking boards but I'm not sure if they're comparable.
LCMXO2-1200ZE http://ie.farnell.com/lattice-semiconductor/lcmxo2-1200ze-b-evn/board-breakout-machxo2-1200ze/dp/2253066
LCMXO2280 http://radionics.rs-online.com/web/p/programmable-logic-development-kits/7434788/
 

Offline mikeselectricstuff

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #17 on: May 07, 2013, 03:43:27 pm »

@mikes electricalstuff : whaddayamean no define ?
..in VHDL - I gather Verilog is better in this respect

My main gripe with vhdl is that there is too much typing involved ( keyboard pounding) and duplication of work.
[/quote]

Yes, it is a bit typing-heavy - if only you could do #define sl std_logic and #define slv std_logic_vector....
Quote
You need to define all signals twice.
huh?
Quote
If x is an output you cannot write x=x+1 as you cannot read back... You need to define an intermediate signal to bring the output back in. Then there is the muckery with all the libraries. Std-blabla ieee-blabla. There is maths , boolean and you need to provide the marshalling between them. Synopsis has its ow libraries that are not compatible with ieee and it all becomes soup...
You can do x=x+1 to a signal in VHDL - are you maybe talking about ports?
Quote

Verilog was written fro. The beginning to describe logic. So it doesn't need all the curly-wurly bits.

Both languages produce exactly the same output and are equals.
Vhdl is just the grumpy sauerkraut snorting german while verilog is a friendly british grandma 'care for a crumpet and some tea ? '
Another comparison I got the feeling of was that VHDL is like Pascal and Verilog is like C, in terms of type-checking and being able to get into trouble very easily.
Quote
You pick what you want to deal with every day .. The saur kraut , or tea and crumpets.
maybe I should look at Verilog next time I have a more serious project -  I typically only do FPGA stuff every couple of years so tend to stick with what I know - projects are often on silly timescales (like 2 weeks for PCB, FPGA, firmware and build of boards) & fighting with general devtool and programmer issues tend to leave no time to learn a new language.
The only reason I went for VHDL originally a few years ago was I found a good book.
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Offline mikeselectricstuff

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #18 on: May 07, 2013, 03:50:19 pm »
The Lattice LCMXO2-7000HE-B-EVN board is in your budget and has onboard programmer. No peripherals though.

Is there a source for these apart from Digikey? Rs and Farnell both stock similar looking boards but I'm not sure if they're comparable.
LCMXO2-1200ZE http://ie.farnell.com/lattice-semiconductor/lcmxo2-1200ze-b-evn/board-breakout-machxo2-1200ze/dp/2253066
LCMXO2280 http://radionics.rs-online.com/web/p/programmable-logic-development-kits/7434788/
Something to be aware of is they changed the FPGA, and hence the board part no from the 1200 to the 7000, so some websites have some confused part numbers - Farnell show the 1200 one as awaiting delivery.
mouser definitely have it.
http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3d

 The 2280 is the old XO family (unfortunate that the part no starts with 2 - this confused me for a while as the PCBs  loko similar).
 
BTW once you get started, I suggest avoiding using the programmer tool in Lattice Diamond - it's slow and can be flaky in SRAM mode- ISPVM (from Lattice website) is much faster (2 secs vs. 6 secs SRAM  program time).
Youtube channel:Taking wierd stuff apart. Very apart.
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Offline free_electron

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #19 on: May 07, 2013, 04:28:12 pm »
Quote
You need to define all signals twice.
huh?
once in the  entity once in architecture.. it's all duplication of work.


Quote
You can do x=x+1 to a signal in VHDL - are you maybe talking about ports?
yep. if x is a registered output port you need intermediate hoop-jumping to get it back in. that's stupid.

there is a t less keyboard pounding in verilog. you also don't have these annoying problems with the library incompatibilites. some people use the std_logic some use the std_maths and then you try to synthsize and you get barfed on by the compiler ...

for a bit of fun : take a look at this topic :
http://www.alteraforum.com/forum/showthread.php?t=23803

imodule countr(input clk,enable,reset,
              ouput reg [15:0] count)

reg [15:0] internalcntr;
always_ff @(posedge clk)begin
  if (!&internalcounter) internalcounter <=internalcounter +1;
  if(!enable) begin
     if (|internalcounter) count <=internalcounter;
     internalcounter <=0;
  end if
  if(reset) begin
     count <=0;
     internalcounter <=0;
  end
end
endmodule


the !& basically logically ANDS together all bits ( so it creates a 16 input AND gate , combining all bits in the counter) as long as the output of that ANd is LOW ( ! operator) we count up. when we hit all '1' the count will seize..

as this is scheduled code the counter can be running always. since the 'enable' is tested later it has overriding power. that clause actually keeps the counter at zero unless we release it. i test if there is something in 'internalcounter'. if there is i copy it over to output. if there is nothing i don;t copy it over. this has the effect of 'holding' the last non-zero number.

and finally the reset has the largest hammer. if that one kicks in i don;t care what any other rules said : wipe it all.

Here is one of the disaster contests i talked about. this was organized by SNUg ( Synopsys Users group )
http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
there are several others. one they had to make an alarm clock including mulitplexd 4x7 segment . they had 30 minutes. the veriloggers were all done. vhdl ? nil ...  as their code wouldn't synthesize..
« Last Edit: May 07, 2013, 04:40:04 pm by free_electron »
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Offline krivx

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #20 on: May 07, 2013, 04:43:26 pm »

Something to be aware of is they changed the FPGA, and hence the board part no from the 1200 to the 7000, so some websites have some confused part numbers - Farnell show the 1200 one as awaiting delivery.
mouser definitely have it.
http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3d

 The 2280 is the old XO family (unfortunate that the part no starts with 2 - this confused me for a while as the PCBs  loko similar).
 
BTW once you get started, I suggest avoiding using the programmer tool in Lattice Diamond - it's slow and can be flaky in SRAM mode- ISPVM (from Lattice website) is much faster (2 secs vs. 6 secs SRAM  program time).

Thanks. Unfortunately shipping from Mouser is almost as much as the board. I might have to wait and combine a few orders.
 

Online TerminalJack505

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #21 on: May 07, 2013, 04:46:10 pm »
Most of my experience is with VHDL.  I remember reading somewhere that Verilog was C-like.  I thought, "Awesome!  I'll have to check it out."  It seems to me they forgot the important parts of C language. 

Who in their right mind would throw away the bracketing notation and use Pascal/SQL/Ada-style block notation?

Oh well.  At least it isn't Shell script notation:

Code: [Select]
if [ blah ] ; then
   case $whatever
      ...
   esac # Huh?
fi # Wha... ?

I'll have to do like Mike's thinking about doing and do a project or two in Verilog.  See if I can stomach it a little better than VHDL.
 

Offline nctnico

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #22 on: May 07, 2013, 05:47:33 pm »
The biggest advantage of VHDL is that it is a lot like a programming language. Like Pascal its roots lie in Ada. The thing is that a lot of designers use VHDL to describe logic equations. That takes a lot of typing indeed.

In my experience one should approach an FPGA design as writing a piece of software and just don't care about how it is translated into hardware. VHDL offers a lot of powerful tools like functions and records (the C equivalent of a structs) which make life so much easier. A clever function can replace dozens of lines of code. A record can be used to easely convey a whole bunch of signals throughout a design like passing a pointer to a struct in C. It really pays off to study VHDL's advanced features.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline mikeselectricstuff

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #23 on: May 07, 2013, 06:00:37 pm »

Something to be aware of is they changed the FPGA, and hence the board part no from the 1200 to the 7000, so some websites have some confused part numbers - Farnell show the 1200 one as awaiting delivery.
mouser definitely have it.
http://uk.mouser.com/ProductDetail/Lattice/LCMXO2-7000HE-B-EVN/?qs=sGAEpiMZZMurtJ7VwBTl0fuXvMOPgNe8hSHI90CFJ0k%3d

 The 2280 is the old XO family (unfortunate that the part no starts with 2 - this confused me for a while as the PCBs  loko similar).
 
BTW once you get started, I suggest avoiding using the programmer tool in Lattice Diamond - it's slow and can be flaky in SRAM mode- ISPVM (from Lattice website) is much faster (2 secs vs. 6 secs SRAM  program time).

Thanks. Unfortunately shipping from Mouser is almost as much as the board. I might have to wait and combine a few orders.
Lattice do have their own store, but  I suspect shipping may also be an issue. May also be worth prodding farnell - it could be that the part number change has confused their system

 
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Mike's Electric Stuff: High voltage, vintage electronics etc.
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Offline jahonen

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Re: Getting started with FPGAs: choices on HDL and devboards
« Reply #24 on: May 07, 2013, 06:12:38 pm »
My main gripe with vhdl is that there is too much typing involved ( keyboard pounding) and duplication of work. You need to define all signals twice.
If x is an output you cannot write x=x+1 as you cannot read back... You need to define an intermediate signal to bring the output back in.

But if you make the port type buffer instead of out, it works just fine. No need to use an extra signal.

Regards,
Janne
 


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