Getting started with FPGAs: choices on HDL and devboards

[vvanders]

Bring on the holy wars!

As far as a decent Verilog reference I found this PDF via fpga4fun to be pretty good with a nice heavy emphasis on synthesis.

[fpga]

I don't think it's too hard to move from one to the other. The syntax is a bit different and VHDL is strongly typed, but the concepts as they apply to FPGAs.

Bad mistake. VHDL is a full blown programming language where Verilog is a netlist format. If you are used to using the full potential of VHDL then switching to Verilog will be a cold shower.

This reminds me of the days that people were comparing Pascal with C, then shortly later Modula with C++. Since C and C++ permit accessing memory contents directly via pointers, they were declared as very low level languages, not suitable for high level software development. I wonder how many Modula programmers are gainfully employed today? If it weren't for Borland Delphi, Pascal would be history too.

Modern versions of both VHDL and Verilog / SystemVerilog, can each do everything that the other can do. Just a quick search of who uses what -- ARM, Infineon, and NXP use VHDL, Intel, AMD, Broadcom, Qualcom, and Cisco use Verilog or SystemVerilog. So clearly either language can be used to get the job done.

The major difference that others in this blog have so very well pointed out is that VHDL is a very strict language that forces you to code in a certain way. Verilog, on the other hand, offers freedom of expression -- it doesn't care how you code, kind of like C and C++ for programming.

One fallacy is to rely on the language semantics as a guarantee of good code. Simply choosing to use VHDL will not assure that your design is correctly implemented. The very strict type enforcement and the duplication via declaration and definition may help catch novice bugs, but in practice such bugs are easy to spot by an experienced engineer, but the extra code overhead will bury and obscure the complex bugs.

In my opinion, the language that permits expressing one's intent in the most elegant, readable and concise form is the clear winner.

From what I've seen SystemVerilog is the language that has everything worth keeping and has the highest level of adoption today. This is not to say that VHDL is going away any time soon, but more and more complex designs using VHDL will be mixed language with some IP in Verilog or SystemVerilog. A decade ago, Xilinx IP was mostly all VHDL, but today much of the newer IP is in Verilog while the older IP is in VHDL. As a result, complex Xilinx designs today are mixed language, granted that you only need to know one of the languages to implement your designs.

So finding fault in one language over the other is purely religious. If you have a choice, then the best one is always the one that most closely aligns with you philosophy, otherwise, it's the language that your employer has chosen for you.

[glatocha]

Yeah I think generally it will go down to what book I will get and in which language is the demo software for my board written, so you can take a look and copy some parts.

Another thing, I checked out the Xilinx ISE and there is a function that you can simply draw the schematic. Use standard gates or the 74 chips series.
Is this used at all in the industry? I think for some simple decoding or some registers it is fast and convenient.

[joelby]

Basically, no. Schematic capture is not very well supported in the latest releases of ISE, and as far as I can tell nobody uses it seriously except for supporting legacy designs.

Well-structured HDL is much quicker to write and easier to comprehend and test.

[MacAttak]

Even just going through the basic stopwatch tutorial for ISE that covers schematic capture alongside VHDL and Verilog, I walked away thinking "who in their right mind would choose to use schematic capture for this?". As a tool, it just didn't really seem to fit the purpose.

Both VHDL and Verilog are significantly easier to understand than schematic (once you start digging below the very topmost layers of a design). At least for me (and take that with a grain of salt, because I'm far from a professional with these tools). That may be because I come from a programming background - text is often easier to grok than drawings for complex systems.

And I think the modern toolchains don't really care - they will let you use whichever you prefer. At least ISE does... I don't have experience with the others but presume they all do.

[c4757p]

Basically, no. Schematic capture is not very well supported in the latest releases of ISE, and as far as I can tell nobody uses it seriously except for supporting legacy designs.

I implemented an entire CPU in the ISE 14 schematic capture last semester for my intro Digital Logic Design course term project. (We were required to use schematic capture, god knows why, and I wanted to do a CPU.) Not very well supported how?

[joelby]

I implemented an entire CPU in the ISE 14 schematic capture last semester for my intro Digital Logic Design course term project. (We were required to use schematic capture, god knows why, and I wanted to do a CPU.) Not very well supported how?

From memory, some of the primitives supported by newer FPGA families are missing, the tool hasn't been updated in years, and I don't think traditional schematic capture is supported in Vivado at all (but don't quote me on that).

[c4757p]

Ah. I wasn't doing anything on a newer FPGA, so I didn't know that. The only bad impression I got from it is that the capture system itself was shitty, but by the end of fourteen pages or so of schematics I was even getting used to that steaming turd.

[nctnico]

I don't think it's too hard to move from one to the other. The syntax is a bit different and VHDL is strongly typed, but the concepts as they apply to FPGAs.

Bad mistake. VHDL is a full blown programming language where Verilog is a netlist format. If you are used to using the full potential of VHDL then switching to Verilog will be a cold shower.

This reminds me of the days that people were comparing Pascal with C, then shortly later Modula with C++. Since C and C++ permit accessing memory contents directly via pointers, they were declared as very low level languages, not suitable for high level software development. I wonder how many

From what I've seen SystemVerilog is the language that has everything worth keeping and has the highest level of adoption today. This is not to say that VHDL is going away any time soon, but more and more complex designs using VHDL will be mixed language with some IP in Verilog or SystemVerilog.

The catch is that the old school Verilog is no match for VHDL if you know how to use VHDL to its maximum potential. I'm not saying VHDL is the best language there will ever be for FPGA or logic design in general. If you have to make do with what you have available (Verilog or VHDL) I'd recommend VHDL.

Now SystemVerilog is a whole different beast. I must admit I've never looked into it but from what I've read so far it has all the advanced features of VHDL without the obfustigated syntax. So it makes sense to try SystemVerilog first if the tools support it.

[fpga]

I don't think it's too hard to move from one to the other. The syntax is a bit different and VHDL is strongly typed, but the concepts as they apply to FPGAs.

Bad mistake. VHDL is a full blown programming language where Verilog is a netlist format. If you are used to using the full potential of VHDL then switching to Verilog will be a cold shower.

This reminds me of the days that people were comparing Pascal with C, then shortly later Modula with C++. Since C and C++ permit accessing memory contents directly via pointers, they were declared as very low level languages, not suitable for high level software development. I wonder how many

From what I've seen SystemVerilog is the language that has everything worth keeping and has the highest level of adoption today. This is not to say that VHDL is going away any time soon, but more and more complex designs using VHDL will be mixed language with some IP in Verilog or SystemVerilog.

The catch is that the old school Verilog is no match for VHDL if you know how to use VHDL to its maximum potential. I'm not saying VHDL is the best language there will ever be for FPGA or logic design in general. If you have to make do with what you have available (Verilog or VHDL) I'd recommend VHDL.

Now SystemVerilog is a whole different beast. I must admit I've never looked into it but from what I've read so far it has all the advanced features of VHDL without the obfustigated syntax. So it makes sense to try SystemVerilog first if the tools support it.

First of all, if you are going to draw a comparison, make sure you are comparing the items from the same time era; don't compare modern VHDL with Verilog from the early 90's. There's nothing old school with today's Verilog. In fact, VHDL is older than Verilog. Second, make sure you have knowledge of what you are comparing. Both languages are used very successfully today by very successful companies. Neither is deficient in implementing complex circuits such the microprocessors in your PC, Mac, or iPhone. The differences lie elsewhere. For a quick feel of what the languages are like, look them up on Wikipedia.

If you are just starting out learning digital design, my suggestion is to do all three -- implement in VHDL, Verilog, and in schematics. Then build the design on your chosen FPGA and test it out. Also learn how to write a testbench and use a simulator. If this becomes your career, you will be far better off if you are well versed in both VHDL and Verilog. You will quickly see that doing anything of any complexity becomes very tedious in schematics. Schematics are best for board design. But make sure that you are able to represent simple clocked circuits and boolean expressions in schematics since this is what will be asked during interviews.

If you are choosing a language as a career choice, search through the job listings of companies you are interested in working for. Often they specify or strongly hint which language they are using.

Finally, SystemVerilog is a superset of Verilog much like C++ is a superset of C. Most of the object oriented stuff in SystemVerilog applies only to simulation testbenches and the synthesizeable subset is basically Verilog.

[marshallh]

Just keep in mind that for all his fpga advice, he has only written a counter...
And I hope he doesn't stop posting, because that would deprive another fpga discussion channel some much needed comedy

[glatocha]

thank you guys for contributing in this topic. Interesting opinions.

New question:
What is the smallest pin count FPGA on the market. I only find TQFP144. A little unfriendly startup.

And can anyone list known FPGAs with internal configuration memory:
 - Xilinx Spartan - 3AN
 - Latice XP2
 - Actel Fusion, ProASCI3, Igloo

Is any of new Xilinx non volatile?
Is any Altera option or other producers?

[nctnico]

The catch is that the old school Verilog is no match for VHDL if you know how to use VHDL to its maximum potential. I'm not saying VHDL is the best language there will ever be for FPGA or logic design in general. If you have to make do with what you have available (Verilog or VHDL) I'd recommend VHDL.

Now SystemVerilog is a whole different beast. I must admit I've never looked into it but from what I've read so far it has all the advanced features of VHDL without the obfustigated syntax. So it makes sense to try SystemVerilog first if the tools support it.

First of all, if you are going to draw a comparison, make sure you are comparing the items from the same time era; don't compare modern VHDL with Verilog from the early 90's. There's nothing old school with today's Verilog. In fact, VHDL is older than Verilog. Second, make sure you have knowledge

This is turning into a semantic discussion. What I'm saying is that if the tools support SystemVerilog then use that. If not then use VHDL. I have no idea which tools the OP may end up with. Maybe its some old commercial software package bought 10 years ago.

@marshallh: I typed that the first thing I ever made on a CPLD was a counter. In the 20 years after that I have developed lots of complicated CPLD and FPGA designs.

[mikeselectricstuff]

thank you guys for contributing in this topic. Interesting opinions.

New question:
What is the smallest pin count FPGA on the market. I only find TQFP144. A little unfriendly startup.

And can anyone list known FPGAs with internal configuration memory:
 - Xilinx Spartan - 3AN
 - Latice XP2
 - Actel Fusion, ProASCI3, Igloo

Is any of new Xilinx non volatile?
Is any Altera option or other producers?

There is a huge unexplained gap in FPGA pin counts. There are some 32 pin QFNs (Lattice XO2, and I think Ice40) , and also 25 ball WLCSP and 64BGA in teh XO2 range, but pretty much nothing from the major players until you get to 100 pin.  I suspect it may have originated from die sizes on early devices, but seems pretty ridiculous nowadays.
I thing Microsemi have some smaller packages.

Lattice XO2 has internal config (and core regulator if you want) - although the XO series started off as basically CPLD, the upper end XO2's are much more like FPGAs than CPLDs

[mrflibble]

Interesting opinions.

That was what I was thinking.

What is the smallest pin count FPGA on the market. I only find TQFP144. A little unfriendly startup.

If you don't mind QFN's there's the AGL030 in a QFN-48 package. The ICE40 also has some low pincount devices, although if you want lower than 48 ... then it's a 36 ball bga device. Which is probably more unfriendly than the TQFP144.

The TQFP144 might actually end up being easier than the QFN though. As in easier to route out all the connections, assuming you don't need all the IO's. That, and you actually see the pins so reworking a little mistake is going to be easier than QFN. There's also some VQPF100's in the Igloo & ICE40 series.

Is suspect that if you want smallest number of "pins" then you'll end up with bga. If you want something where you can still see the pins for easy mucking about then it's going to be TQFP/VQFN 100 pins or more.

There are some 32 pin QFNs (Lattice XO2, and I think Ice40) ,

Which ICE40 is in QFN-32? I vaguely recall the smallest being one of those double row bigger QFN's (80-ish pins) when I went over the list, but I could very well be wrong.

*checks datasheet* Ah, you're right. The LP384 is indeed in QFN-32. I guess I immediately forgot about that one again because it doesn't have a PLL.

So if glatocha doesn't mind QFN and doesn't require a PLL then that might be a nice option.

[gregariz]

I am in a similar situation to Ivan and was about to buy a Papilo pro from Gadget Factoryhttp://papilio.cc/index.php?n=Papilio.PapilioPro Spartan LX6 with 64 Mb SDRAM. What do the experienced folks think?

I have the Papilio board.. yes its Xilinx but the parts are easy to get if you are doing your own thing. The upside with the Papilio board is the free tutorial book (VHDL) by Mike Field that seems pretty good if you are starting out. You'd probably want the logic start board as well though. Its an alternative to the Digilent Basys board although its a bit cheaper. I ended up getting the arcade board and turning it into a Galaga game console when I finished with it.

Depending on what you want to do it may be easier and cheaper to work with a small CPLD if you don't need the logic space but still want to learn VHDL.

[mrflibble]

Depending on what you want to do it may be easier and cheaper to work with a small CPLD if you don't need the logic space but still want to learn VHDL.

It indeed depends on what you want. If you are really new to this and don't know what you don't know, and also don't know precisely what you're going to do as a first project ... best get an fpga board instead of cpld. With a CPLD you run out of flip-flops real quick. For some things that's no biggie, but if the moment you want to do something that requires a reasonable amount of memory ... *poof* ran out of FFs.

Case in point, I started out on a cpld board (Altera MAX 3000A). And while it was perfectly good to learn all sorts of thing regarding programmable logic, some things I would have liked to do just weren't going to fit.

So I'd suggest that if you don't know exactly what type of design you're going to try out first, get a fpga board since it's a bit more versatile in the type of design you can try. Besides, with modern fpga's you also get all sorts of extra goodies like PLL/DCM to generate clocks, which also can be quite handy.

[nctnico]

Depending on what you want to do it may be easier and cheaper to work with a small CPLD if you don't need the logic space but still want to learn VHDL.

It indeed depends on what you want. If you are really new to this and don't know what you don't know, and also don't know precisely what you're going to do as a first project ... best get an fpga board instead of cpld. With a CPLD you run out of flip-flops real quick. For some things that's no biggie, but if the moment you want to do something that requires a reasonable amount of memory ... *poof* ran out of FFs.

You can always use an external SRAM. I did several CRT/DSTN to TFT conversion designs using a Xilinx XC9500XL CPLD. The image is kept in the SRAM and displayed onto the TFT screen.

[legacy]

Avoid the Xilinx tools like the plague (yes even they know ISE is crap).
Don't be another one that ignores my advice then bawws at how hard fpgas are unnecessarily

Why Xilinx is so bad ?

[mrflibble]

It indeed depends on what you want. If you are really new to this and don't know what you don't know, and also don't know precisely what you're going to do as a first project ... best get an fpga board instead of cpld. With a CPLD you run out of flip-flops real quick. For some things that's no biggie, but if the moment you want to do something that requires a reasonable amount of memory ... *poof* ran out of FFs.

You can always use an external SRAM. I did several CRT/DSTN to TFT conversion designs using a Xilinx XC9500XL CPLD. The image is kept in the SRAM and displayed onto the TFT screen.

And I did several <fill_in_stuff_here> on a coolrunner II. That doesn't change the fact that cpld's typically have a low storage element to combinational logic ratio. Which is fine for some things, but not for others. The display controller scenario is where you can stream in your data, and then only need a limited amount of internal (cpld/fpga) to do the actual processing. My point is that as soon as you need more than a few FFs to simultaneously hold data so you can actually do processing on it, with the cpld you are boned.

[Hardcorefs]

Avoid the Xilinx tools like the plague (yes even they know ISE is crap).
Don't be another one that ignores my advice then bawws at how hard fpgas are unnecessarily

Why Xilinx is so bad ?

If I was being vindictive I would say the tools are  programmed by morons.....

All the underlying tools are actually command line programs that have seen better days, that in itself should be a warning for ANY  shell based GUI.
After all how can the  GUI get to the fundamental data needed to correctly control the process, without having to parse a shit load of  CR/LF terminated crap.

To round out these overly expensive tools they have built the GUI out of java, don't get me wrong... java is excellent I use it myself in a BIG way....
However in the hands of a 'mad-man- C++ programmer it is a disaster, specifically , creating and removing 'objects' in java is VERY expensive.

So you have a GUI that calls "Subroutines" (subroutines are good.... they allow code reuse), unfortunately the idiots over at xilinx, decide to 'create' a lot of NEW object inside these subroutines, then don't properly release them... and so memory leaks and GC events breed faster than roaches... (just fire up the java debugger when their front end is running.....and watch the upward sawtooth GC)


 That is just on the technical side.....

On the VHDL side, WHY O WHY in this day and age to I have to repeatedly COMPILE from scratch, even if I add a blank line?
Because the idiots take the timestamp as being the deciding factor if the VHDL has changed, and when you are on a 16 HR compile time it is no joke....

WHY can I not have VHDL that compiles into small modules (like it does NATURALLY)
, then be able to DRAG & DROP PRE compiled logic sections to be linked together.
 If I have a UART that communicates at 19200 with the outside world but stores the shit in memory.. do I really give a rats ass if the link between the UART and the memory cannot function at the  "global" clock timing of 5-10ns.. no...  but WTF do i then have to get my "magic" book out and start typing  Martian.. so as to enter a timing constraint to tell the compiler I don't give a rats ass....

WHY can I not use D&D then  have a parameter between the logic links doing this.....
" Hay pls link my 500MHZ memory module with my 100Mhz Uart ... using this  netlist with the timing link at ~10MHZ"
"I would prefer if the memory module sit in subsection A and the UART sits in subsection B" using these external pins...."



Next up......
Plan Ahead........(for your early stressed out retirement)
This allows you to set "different" compiler options to fine the BEST route/ timing, but..... lets say you find a design that compiles at 120MHZ, but the timing says "shit, i can get this upto 150MHZ"

So you reset your DCM inputs to use the new clock speed and  run plan ahead.........BAM YOU ARE DEAD,
Plan ahead has NO  source control......., so unless you are a genius that can remember EVERY change you made.... you cannot quickly roll back to a previous design... even if it is a single line change such as:

CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32
to
CLKFX_MULTIPLY => 15, -- Can be any integer from 2 to 32

AND just to make your life REAL difficult... because you changed a SINGLE VHDL statement , EVERYTHING has to be re-compiled... even un-associated modules. (yep i know I can drop down to the command line with my martian incantations and patch bits of files together using TCL, but WhereTF is the source control and a record of what I did to achieve the design)

WTF can they not integrate GIT into the JAVA GUI?


All this and more can be yours for $5,000 per seat....

Final handy tip....

Reboot your computer BEFORE running a long compile... it can fails silently halfway through...
I.E
No reboot
>20hours no result... java crashes silently with out of memory... only Java debugger can spot

reboot
4hours fully compiled....

[glatocha]

hmm,

you wrote this about ISE or Vivado.

How does the Altera and Lattice in comparison?

[legacy]

@Hardcorefs

about this issue

On the VHDL side, WHY O WHY in this day and age to I have to repeatedly COMPILE from scratch, even if I add a blank line?

what about Altera ?

[nuhamind2]

I choose Altera just because the avalaibility of cheap board and programmer from ebay.

[nctnico]

Avoid the Xilinx tools like the plague (yes even they know ISE is crap).
Don't be another one that ignores my advice then bawws at how hard fpgas are unnecessarily

Why Xilinx is so bad ?

Just ignore. Every tool has a learning curve and it takes time to understand the principles that are behind it. I get along with ISE just fine but I have been using it for almost a decade. If you are new to it then it is wise to follow some tutorials and watch some videos.