Avoid the Xilinx tools like the plague (yes even they know ISE is crap).
Don't be another one that ignores my advice then bawws at how hard fpgas are unnecessarily
Why Xilinx is so bad ?
If I was being vindictive I would say the tools are programmed by morons.....
All the underlying tools are actually command line programs that have seen better days, that in itself should be a warning for ANY shell based GUI.
After all how can the GUI get to the fundamental data needed to correctly control the process, without having to parse a shit load of CR/LF terminated crap.
To round out these overly expensive tools they have built the GUI out of java, don't get me wrong... java is excellent I use it myself in a BIG way....
However in the hands of a 'mad-man- C++ programmer it is a disaster, specifically , creating and removing 'objects' in java is VERY expensive.
So you have a GUI that calls "Subroutines" (subroutines are good.... they allow code reuse), unfortunately the idiots over at xilinx, decide to 'create' a lot of NEW object inside these subroutines, then don't properly release them... and so memory leaks and GC events breed faster than roaches... (just fire up the java debugger when their front end is running.....and watch the upward sawtooth GC)
That is just on the technical side.....
On the VHDL side, WHY O WHY in this day and age to I have to repeatedly COMPILE from scratch, even if I add a blank line?
Because the idiots take the timestamp as being the deciding factor if the VHDL has changed, and when you are on a 16 HR compile time it is no joke....
WHY can I not have VHDL that compiles into small modules (like it does NATURALLY)
, then be able to DRAG & DROP PRE compiled logic sections to be linked together.
If I have a UART that communicates at 19200 with the outside world but stores the shit in memory.. do I really give a rats ass if the link between the UART and the memory cannot function at the "global" clock timing of 5-10ns.. no... but WTF do i then have to get my "magic" book out and start typing Martian.. so as to enter a timing constraint to tell the compiler I don't give a rats ass....
WHY can I not use D&D then have a parameter between the logic links doing this.....
" Hay pls link my 500MHZ memory module with my 100Mhz Uart ... using this netlist with the timing link at ~10MHZ"
"I would prefer if the memory module sit in subsection A and the UART sits in subsection B" using these external pins...."
Next up......
Plan Ahead........(for your early stressed out retirement)
This allows you to set "different" compiler options to fine the BEST route/ timing, but..... lets say you find a design that compiles at 120MHZ, but the timing says "shit, i can get this upto 150MHZ"
So you reset your DCM inputs to use the new clock speed and run plan ahead.........BAM YOU ARE DEAD,
Plan ahead has NO source control......., so unless you are a genius that can remember EVERY change you made.... you cannot quickly roll back to a previous design... even if it is a single line change such as:
CLKFX_MULTIPLY => 12, -- Can be any integer from 2 to 32
to
CLKFX_MULTIPLY => 15, -- Can be any integer from 2 to 32
AND just to make your life REAL difficult... because you changed a SINGLE VHDL statement , EVERYTHING has to be re-compiled... even un-associated modules. (yep i know I can drop down to the command line with my martian incantations and patch bits of files together using TCL, but WhereTF is the source control and a record of what I did to achieve the design)
WTF can they not integrate GIT into the JAVA GUI?
All this and more can be yours for $5,000 per seat....
Final handy tip....
Reboot your computer BEFORE running a long compile... it can fails silently halfway through...
I.E
No reboot
>20hours no result... java crashes silently with out of memory... only Java debugger can spot
reboot
4hours fully compiled....