Unfortunately, nothing yet available comparable on RISC-V, just GD32VF103 :'
There are now two ESP32s announced that are purely RISC-V, along with the earlier one with the main core still xtensa plus a low power RISC-V core.
Renesas is getting into RISC-V, and announced partnerships with Andes six months ago and SiFive this month.
ST Microelectronics has been advertising for a senior RISC-V core designer.
Of course anyone who is just starting now is not going to have chips for retail sale for 12 to 24 months.
I think the first ESP32s have already come through. There is also the similar BL602 from Bouffalo Lab which is already available.
On another level, the Allwinner D1 is already in mass-production. I heard 5 million chips in the first batch. It's aimed at around the ARM A7, A35, A53 point in the market. A few months ago Sipeed and Pine64 announced plans for Linux SBCs using it at $12.50 and "under $10" price points. They are still planning to have SBCs soon, but the component pricing and supply situation might not let them hit those prices right now. That's a 1 GHz single core RV64 chip with vector unit. I think boards at that price level would probably have 256 MB of RAM.
For about the last week I've had ssh access to Allwiner's EVB for the chip, one at RVboards and starting yesterday one at Sipeed. Before the ssh access I was able for a few days to send test binaries to a Sipeed engineer and he was running them for me. At the start Sipeed didn't know whether Allwinner had paid Alibaba/T-Head for the vector unit option, as while they have a couple of boards from Allwinner they don't have the datasheet yet.
My early test programs proved that the D1 does in fact have a vector unit with 32 registers of 128 bits each, and ALUs handling 8, 16, and 32 bit integers and 32 bit FP.
With the way the RISC-V Vector ISA works, if you don't need 32 variables in your vector loop then you can instead reconfigure it to 16 registers of 256 bits each, or 8 registers of 512 bits each, or 4 registers of 1024 bits each. The memory bus and ALU are still only 128 bits wide, but you can keep them busier as the instruction fetch and scalar bookkeeping become proportionally less.
Unfortunately as the V extension 1.0 has not been frozen and ratified yet and yet this is a real chip already existing, it implements a draft version (0.7.1 from June 2019) of the vector spec. There are many many incompatibilities between draft 0.7.1 and the current draft 0.10 in both instruction mnemonics, semantics, and binary encodings.
However I have confirmed that at least memcpy() can be coded to be binary compatible (and maximally efficient) between 0.7.1 and what should become 1.0 later this northern summer. I'll shortly be checking other byte-oriented code such as strlen(), strcpy() etc. Anything using 16 or 32 bit elements is for sure not binary compatible as the format of the VTYPE CSR (and the type in the VSETVL{I} instructions) has changed.
I'm actually hoping to persuade people to change that back, as while the new format is tidier and there is no promise of backwards compatibility before 1.0 it's a pretty trivial thing.
Despite the incompatibility in details, the overall structure of assembly language code in 0.7.1 is the same and it's usually pretty trivial to convert code from one to the other. It's also an awesome Vector ISA. Much much better than using MMX, SSE, AVX, AVX512. Similar to ARM SVE, but normal people won't have access to any SVE chips for ... another 12 months at least?
I did tests of the standard glibc memcpy and strcpy vs vector versions:
http://hoult.org/d1_memcpy.txthttp://hoult.org/d1_strcpy.txtVectorised memcpy is 2x faster than the standard glibc one at small sizes, rising to near 4x at 64 bytes size, and staying near 2x until the copy is larger than L1 cache.
It's also 24 bytes of code instead of 622 bytes.
ARM and x86 systems are of course using AVX or NEON in their memcpy implementations. Those are fast, but they still take a *lot* of code to deal with alignment and sizes that are not a multiple of the vector register size.
The RISC-V Vector code handles all the corner cases within that 24 byte function. (40 bytes for strcpy)
If anyone would like to try out a D1 Eval Board, Sipeed and RVboards are offering ssh logins:
https://twitter.com/cpswang/status/1385112512329175041https://twitter.com/SipeedIO/status/1387608606757978116Sipeed perhaps rather foolishly simply published the password in that tweet, so there has been some problem with vandals. Which is why I'm mostly using the other one myself.
RISC-V International has today offered to send free boards to interested early adopters. I'm not sure exactly how they are deciding who is qualified, but here's the info:
https://www.hackster.io/news/risc-v-international-offers-academics-individuals-free-development-boards-with-up-to-16gb-of-ram-e46c7b15b4achttps://docs.google.com/forms/d/e/1FAIpQLSe1xKtGTKA3gsGxx1MjLgupYdeoMf5XtDxnOgKYjQyJDk52ig/viewform
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