Good FPGA tutorials

[MattSR]

Hi Guys,

I would like to learn more about the in's and outs of FPGA fabric design and implementation. I have a good grasp of basic electronics and want to understand more about the actual design process that goes into making an FPGA core work.. Can anyone point me in the direction of some good tutorials? There was a good article in a british magazine I saw in the newsagent the other day, but the cost of the mag was too high to justify buying it for one article...

Cheers,
Matt

[olsenn]

Check out LBE Books (Learning By Example):http://www.lbebooks.com/booksandkits-HWDesignVerilog.htm

Their Verilog/VHDL books, Basic Digital Design and Advanced Digital design, are incredible. They use Digilent (Xilinx) dev boards, but both the concepts and the coding are not unique to those boards (should work for any FPGA).

[mrflibble]

The traditional tutorial: http://www.asic-world.com/verilog/veritut.html

And don't wait too long with My First Testbench: http://www.asic-world.com/verilog/art_testbench_writing.html

[MattSR]

Thanks guys,

I've been using Ettus Research's USRP1 for a few years now, and the magic inside the FGPA has alluded me. I understand what it does in terms of the application and DSP layer and now I want to figure out how these things work.

Cheers
Matt

[free_electron]

the best verilog book is the one by Bhasker. Verilog for synthesis.
no frills , straight to the point and explained by showing you exactly WHAT is being generated for the constructs. this is one of the few books that touches the concept of scheduling and how the synthesizer works. Understanding the fundamental synthesis concept allows you to write code in a style that guarantees almost 100% first time right. You won;t run into undefined pathways, latch inferral and other 'gotcha's. Use the synthesizer.

Very few people understand how the synth works and you end up with massive blocks of code full of it-then-else-elseif constructs where none are even needed.

[mrflibble]

the best verilog book is the one by Bhasker. Verilog for synthesis.

You probably mean "Verilog HDL Synthesis, A Practical Primer" from Bhasker, right? In any event I can also recommend Bhasker. My first verilog book was "A Verilog HDL Primer" by Bhasker, and that lend itself pretty well to the learn it from the books approach. One good book of your choosing + assorted random articles on the internet should get you started.

Also, I found some of these papers quite useful to learn from: http://www.sunburst-design.com/papers/

[richcj10]

I like the this website;

http://www.fpga4fun.com/index.html

[marshallh]

Here are some things I've learned, written up for the benefit of some guys I am working with.

http://retroactive.be/verilog_tips.pdf

Comments are welcome

[mrflibble]

Comments are welcome

Looks good. Couple of small things that sprang to mind while reading it:

Clock Domains

... depending on how newby the audience is you may want to define a bit more clearly by what you mean with "edge-synchronous".

Avoiding Metastability

... regarding the synchronizer registers, you may want to give a hint on how to make sure those registers are synthesized as fabric FFs instead of a shift register. Fabric FFs tend to have better metastability characteristics than shift registers.

General: case statements

In addition to always specifying a default ... you may want to point out what style of don't cares best to use. There's a nice Sunburst paper on that...

[Hardcorefs]

HERE:
FPGA design from scratch. Part 1
It covers RIGHT from the start and also covers WHY and how.....
http://svenand.blogdrive.com


Currently the guy is upto Part 93

and
http://www.fpgadeveloper.com

[codeboy2k]

Comments are welcome

Good tips, the content is decent and covers a lot of good ground for best practices. 


Clock Domains

    B. never clock logic using other logic...

this is a good point, new guys often try to divide a clock and use it to clock a series of other modules, so this is good to advise against here. 
However, you should tell why this bad, not just advise against it. (i.e. mention that clocks nets are special, have high fanouts, are routed special so as to reduce skewing, and keep all the logic synchronous, etc; regular logic is often routed as best is available across the fabric and may take long and different routes to reach a destination's clock input on a module, they will be out of sync, timing will be off, etc. Mention that a clock should be divided down using available clock resources, or if logic is used, the output should be fed back into a clock buffer so that it gets onto a clock distribution net for use by other modules.
 

Also, the font was awful on my Linux Mint 14 system. Your PDF is the first PDF I have ever come across that had troubles rendering fonts.

The font just looks blurry and unreadable at a normal zoom (100%).  I don't have this problem with any other PDF, which I can read fine on my monitor.  With your document, I had to zoom it to monster size before it became cleanly rendered, although it was "readable" at smaller zoom settings (above 100%). Maybe you want to see how you are creating the PDF or what fonts you are using?

see below for screencap that I see from the PDF viewer. This is zoomed to 125% using the viewer's zoom settings then I screen capped it off my screen. That's how I see it.



Maybe you need to include the fonts you use in the PDF outfput settings, and my reader substituted a local font here..

[marshallh]

Give it another shot, it would show fine in Adobe but not in Firefox' shite built-in viewer.

[Medo]

Check Cornell ECE5760 lectures on YouTube:

[bradleytron]

HERE:
FPGA design from scratch. Part 1
It covers RIGHT from the start and also covers WHY and how.....
http://svenand.blogdrive.com


Currently the guy is upto Part 93

and
http://www.fpgadeveloper.com

The first link seems to be broken.

[VanitarNordic]

HERE:
FPGA design from scratch. Part 1
It covers RIGHT from the start and also covers WHY and how.....
http://svenand.blogdrive.com


Currently the guy is upto Part 93

and
http://www.fpgadeveloper.com

The first link is broken.

[pyroesp]

The first link seems to be broken.

The first link is broken.

Works fine on chrome...

[MacAttak]

Refresh your browser if you get an error page the first time. Using Chrome on OS X and when I go to the page for the first time it gives an error. Refresh and everything's fine. Does it every time I go to that website after restarting my browser or computer.

[Hardcorefs]

Damn looks like he has taken it down.......

[mrflibble]

Damn looks like he has taken it down.......

Nope, it's there. Host response is just intermittent. In any event, you mean you don't have that site mirrored? O_o