Has anyone used spread spectrum CPU clock modulation, with ETH or USB?

[peter-h]

This is a feature on the STM chips, notably the 32F4 that I am using.

The modulation depth is programmable, up to a 2% deviation.

Obviously a bigger deviation spreads the unwanted spike better...

I wonder if a 2% deviation would mess up ETH or USB?

This partly refers
https://www.eevblog.com/forum/microcontrollers/do-the-480mhz-stm-chips-present-bigger-emc-issues-over-the-168180mhz-ones/

[mikeselectricstuff]

I'd definitely avoid any sort of jittery clock for ethernet - I had issues using a MEMS oscillator on a W5500 chip, causing about 1% packet loss.

[magic]

Is it for the CPU core only or the whole chip, including peripherals?


USB specs are fairly demanding on clock accuracy and IIRC 2% is way out. The exact tolerance depends on speed, you should be able to find detailed information easily.

Practical hardware is somewhat more tolerant, particularly if it's a generation faster than the device. For instance, typical motherboard HS hosts seem to tolerate very dodgy FS clocks, at least in the IN direction. Usual result of clock skew is loss of long packets, or progressively shorter ones if you stray further from nominal bitrate. If it's too bad, I suppose enumeration may fail altogether.

[peter-h]

Looking at how the main PPL and then dividers are set up, I would expect all the peripherals to run off the CPU clock and thus suffer the same frequency modulation.

In reality one would do this only if a lab EMC test fails, and do it only just enough to get the exceedance just below the limit. It's all meaningless anyway because a better choice of cables, the test laptop, etc, makes a big difference.

[magic]

I've done your homework for you

7.1.11 Data Signaling Rate

The high-speed data rate (THSDRAT) is nominally 480.00 Mb/s, with a required bit rate accuracy of ±500 ppm.
For hosts, hubs, and high-speed capable functions, the required data-rate accuracy when transmitting at any
speed is ±0.05% (500 ppm).  The full-speed rate for such hubs and functions is TFDRATHS. The low-speed rate for
such hubs is TLDRATHS (a low-speed function must not support high-speed).

The full-speed data rate is nominally 12.000 Mb/s.  For full-speed only functions, the required data-rate when
transmitting (TFDRATE) is 12.000 Mb/s ±0.25% (2,500 ppm).

The low-speed data rate is nominally 1.50 Mb/s.  For low-speed functions, the required data-rate when
transmitting (TLDRATE) is 1.50 Mb/s ±1.5% (15,000 ppm).  This allows the use of resonators in low cost, low-
speed devices.

You won't get far if you want to stay in spec, unless it's LS.

And problems can be real. An HS device with subtly broken quartz cost me hours of  once...

[peter-h]

Funny that the STM appnote on spread spectrum doesn't mention this at all...

[ataradov]

Ethernet is driven by the (R)MII reference clock, which is usually supplied by the PHY, so it won't be affected by the modulation.

USB HS uses external PHY, which generates its own clock, so also will not be affected.

Full Speed USB would be affected, since 48 MHz clock is derived from the same PLL. But at the lowest modulation depth you still will be within the spec. Assuming everything else is ideal, of course. So, in real life it is better to not use SS if you are using FS/LS USB.

[coppice]

Funny that the STM appnote on spread spectrum doesn't mention this at all...

Most data for devices with a clock spreading mode are vague, as they mostly expect it to be used to work around EMC tests, and not be used in normal operation.

[peter-h]

 
Excellent!