Electronics > Microcontrollers

HDL & custom logic magic

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Dajgoro:
Hi.

A while ago, as a university project I designed(through schematic, not HDL) a CMOS random generator (the chip never got made) and I built a poc prototype out of 4000 series logic, and it worked. So later I wanted to get that same circuit working in a CPLD, but there is a problem. In order for the circuit to work it needs a specific combination of logic gates that really don't make any sense to the optimization algorithm that is used when synthesizing the logic, so it would always turn into a mess and I was never able to get the circuit working like that.

Is there a way to synthesize the logic in the exact way as described so that I can generate the messy logic that perform the entropy magic?

I am using Xilinx ISE.


P.S. I couldn't think for a better name for the topic  ???

free_electron:
In quartus (altera) there is a flag to tell the synthesizer to create the logic as it is given. This flag only affects schematic entry. I use this to uygate skew generators made with chains of inverters and a tree-multiplexer that has equal length pathways.

You can do it also in verilog in quartus by writing the block as a netlist and telling the synthesiser not to touch manual netlists.

You can go even further by then hand placing and routing the critical section.

As for xilinx .. I don't know. Don't use em. Hate ISE.

edavid:
What is the operating principle?  Are you relying on relative gate delays or something like that?

Dajgoro:
It is a design of mine, but the basic principle is that I have a bunch of oscillators built from xor gates and trimmed chains of inverters.


--- Quote ---Hate ISE.
--- End quote ---
Why?

nctnico:
You should be ably to use the basic building blocks of the FPGA (LUTs and flipflops). OTOH it would be much better to create a proper HDL version. Look for constraints to have control over timing.

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