The STM32F303CCT6 can operate with two crystals: one watch crystal driving the RTC, and one high-speed crystal driving the processor clock PLL.
I derived two 1Hz signals from the clocks: the slow crystal is divided down to provide the 1Hz clock for the RTC. The fast crystal is PLL'd up to 72MHz, then divided down to provide a millisecond interrupt, and software counts 1000 interrupts to generate another 1Hz clock. Those two slightly disagree with each other.
Questions:
1) Why?
2) Which crystal is at fault? How to tell?
3) How to reduce or eliminate this?