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Help to start with STM3L412 and libopenCM3

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psysc0rpi0n:
Hello,

So, I've been trying to grasp the basics of libopenCM3 libraries to use with my STM32L412CBT chip.
Datasheet
Reference Manual

For now, I'm just trying to use a timer to blink a led. The initial stuff as usual.
I was reading someone's post somewhere on the web about this and tried to replicate some of the steps.

I can confirm with my scope that the following code is bringing the PIN I selected up.


--- Code: ---   rcc_periph_clock_enable(RCC_GPIOB);
   gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0);
   gpio_set_output_options(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_LOW, GPIO0);
   gpio_toggle(GPIOB, GPIO0);
   while(1){
   }

--- End code ---

Now, I started reading about timers and specific clock configuration within the source code of libopenCM3 itself, but it's quite a daunting task for someone with no experience with STM32 chips or libopenCM3, so I need some help to be able to understand how the clock blocks all work together and in isolated conditions and also to be able to use the correct libopenCM3 functions for each task.

I want to use a basic timer (TIM6) which, according to the clock tree from the datasheet below, is affected by the following blocks in the way:


And looking into the code of libopenCM3, I find this function to set the RCC PLL clock register:
rcc_set_main_pll()


--- Code: ---void rcc_set_main_pll (uint32_t source,
       uint32_t pllm,
                       uint32_t plln,
       uint32_t pllp,
       uint32_t pllq,
       uint32_t pllr
)

--- End code ---

But when I look in STM32CubeMX to help me with the dividers and multipliers, it tells me that pllq is not available unless RNG or some IP mode is selected, so, I'm not sure what to send as parameter for this function.
Similar question is for pllp. Reference manual says this is Main PLL division factor for PLLSAICLK (SAI1 clock). But a bit down in the reference manual, it's said that this PLLSAICLK is Not available on STM3L41xxx and STM32L42xxx devices. So, I'm a bit confused here.

Even so, this is what I have for now, but I have no idea this is supposed to be like this and if it will work.

--- Code: ---#include <libopencm3/stm32/gpio.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/timer.h>

int main(void){
   rcc_set_msi_range(0xb0);
   rcc_set_main_pll(RCC_PLLCFGR_PLLSRC_MSI, // [url]https://libopencm3.org/docs/latest/stm32l4/html/l4_2rcc_8h_source.html#l00272[/url]
                    RCC_PLLCFGR_PLLM(1),    // PLLM divider 1, RM0394, page 201
                    40,                     // PLLN divider 40, RM0394, page 201, see also libopencm3 l4/rcc.h file, lines 252 to 255
                                            // STM32CubeMX says it's 40
                    RCC_PLLCFGR_PLLP_DIV7,  // verify this one, RM0394 page 200 and libopencm l4/rcc.h file, lines 246 to 250
                    RCC_PLLCFGR_PLLQ_DIV2,  // verify this one too. It's says in STM32CubeMX that it's not available, ony if IP or
                                            //RNG mode is selected. RM0394 page 200
                    RCC_PLLCFGR_PLLR_DIV2); // PLLR divider 2, RM0394 page 200. STM32CubeMX says it's 2
   rcc_periph_clock_enable(RCC_GPIOB);
   gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO0);
   gpio_set_output_options(GPIOB, GPIO_OTYPE_PP, GPIO_OSPEED_LOW, GPIO0);
   gpio_toggle(GPIOB, GPIO0);
   while(1){
   }
   return 0;
}

--- End code ---


So, if anyone is willing to dive a bit into this with me I would appreciate!

thm_w:
If its not available, should be fine to set it to 0.
You can find some example code here: https://github.com/libopencm3/libopencm3-examples/blob/master/examples/stm32/l4/stm32l476g-disco/basics/basics.c
pllcfg options: http://libopencm3.org/docs/latest/stm32g4/html/group__rcc__pllcfgr__values.html

To me it seems like you've got the right idea.

psysc0rpi0n:

--- Quote from: thm_w on August 03, 2021, 09:55:20 pm ---If its not available, should be fine to set it to 0.
You can find some example code here: https://github.com/libopencm3/libopencm3-examples/blob/master/examples/stm32/l4/stm32l476g-disco/basics/basics.c
pllcfg options: http://libopencm3.org/docs/latest/stm32g4/html/group__rcc__pllcfgr__values.html

To me it seems like you've got the right idea.

--- End quote ---

I'm not sure I started in the right place. I want to use one of the internal clocks that allow me to have the 80Mhz for the timers clock. The image I posted above is from STM32CubeMX, but the one from the datasheet is slightly different.
This is the one I should be sticking to:


The difference is that in the image from my post above (STM32CubeMX), I assumed that the MSI input at the PLL Source Mux, was the block above it called MSI RC. Truth is that I'm not sure this is correct because in the datasheet, block diagram is a bit different.
In STM32CubeMX, the block diagram shows a PLL Source Mux before the PLL block and in the dataseet, I can't see any mux before the PLL block.



So, my question is if the MSI RC block in STM32CubeMX, marked in brown is the same from the one also marked in brown in the datasheet and if this is the input clock source that is feeding the PLL block and that later multiplies and divides to get the 80Mhz out, in the end! (don't mind the frequency and divider/multiplier values shown in the pictures).

Silenos:
I do not understand the red lines in your first pic from rm schematic. If my eyesight is correct, both cube and rm clock tree schematics are the same, and your color clouds in second pic are correct. And MSI connection point commented in red should be "connected before /M...", not "connected after /M...". You sure you haven't mistaken reading a direction of pre-pll mux?

psysc0rpi0n:

--- Quote from: Silenos on August 04, 2021, 09:38:23 am ---I do not understand the red lines in your first pic from rm schematic. If my eyesight is correct, both cube and rm clock tree schematics are the same, and your color clouds in second pic are correct. And MSI connection point commented in red should be "connected before /M...", not "connected after /M...". You sure you haven't mistaken reading a direction of pre-pll mux?

--- End quote ---

The red lines were just to show the path of the blocks that will be influenced by my final goal, which is to get 80Mhz at the end, using TIM6 and PLL.
About the direction of pre-pll mux... I assume pre-pll mux is this:


If so, I didn't notice the arrow pointing in (into) the PLL block. Does this means it is before the PLL block?
Even so, in STM3CubeMX, this PLLM parameter is exiting (after) the PLL block.


Edited;

Ignore, I see now that my mind was kinda blocked/stuck making me see that PLLM parameter was exiting PLL block when it is in fact exiting the PLL source mux (which I think you called pre-pll mux)

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