High Level Synthesis on Lattice FPGAs

[who8877]

Vivado HLS has been great provided you use it sparingly and are aware of its limitations.  However I want to port my design to Lattice devices and the HLS is proving to be an issue.  Does anyone know if there are HLS packages available supporting the ecp5 that are free or cost in the low thousands of dollars?

[Bassman59]

Vivado HLS has been great provided you use it sparingly and are aware of its limitations.  However I want to port my design to Lattice devices and the HLS is proving to be an issue.  Does anyone know if there are HLS packages available supporting the ecp5 that are free or cost in the low thousands of dollars?

A quick web search turned up this. I had not heard of them before looking, so I cannot vouch for anything they say. They do claim “vendor-agnostic HLS” and say that they support Intel, Lattice, Xilinx, Microsemi and Achronix devices (which is to say, all of them).

[who8877]

It looks like they are trying to run a cloud platform - not provide something that spits out synthesized RTL.  Synopsys has the Synphony C Compiler - but when the website doesn't even have a "how to buy" section my assumption is I can't afford it.

[who8877]

Looking again I think I was wrong about the leg up guys - their ad copy is just geared more towards software guys.  I'll give it a try.

[Bassman59]

It looks like they are trying to run a cloud platform - not provide something that spits out synthesized RTL.  Synopsys has the Synphony C Compiler - but when the website doesn't even have a "how to buy" section my assumption is I can't afford it.

If it’s like their version of Symplify Pro that supports high-reliability design (TMR and Hamming coding in synthesis, the latter of which doesn’t work), then your assumption would be correct.