Electronics > Microcontrollers

How do you search for a microcontroller ?

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MarkT:
I'd put another vote in the the Teensy 4, active ecosystem and its faster than you might think with full dual-issue at 600MHz means 1.2GFlops is possible, single single floats.  It also has hardware double floats though a little slower.  Certainly quite an easy platform to get a feel for quickly.

brucehoult:

--- Quote from: MarkT on April 19, 2024, 07:38:08 pm ---I'd put another vote in the the Teensy 4, active ecosystem and its faster than you might think with full dual-issue at 600MHz means 1.2GFlops is possible, single single floats.  It also has hardware double floats though a little slower.  Certainly quite an easy platform to get a feel for quickly.

--- End quote ---

I very much doubt that a M7 can dual-issue FP instructions with other FP instructions. Two int, an int and an FP, something and a branch ... sure.

I think the M7 is somewhat similar to the A53 (other than one being 32 bit and the other 64 of course) in averaging maybe 1.3 IPC on most code, unless it's very carefully hand-written. Newer designs with early&late ALUs in the 2nd pipe (A55, SiFive U74 etc) are more like 1.6 IPC.

The cheaper 1.0 GHz single-issue RISC-V boards (generally with THead C906 core) will run more instructions per second on real code, and are 64 bit, have full FPU (and MMU) and even a 128 bit vector unit.

tellurium:

--- Quote from: luiHS on April 17, 2024, 01:01:41 am ---The NXP RT series is the best, and cheap, I already use the RT1064 for everything. For other jobs that require playing video I use ST's STM32H747.

--- End quote ---

Do you do custom PCB design, or use something ready-to-go like Teensy 4.1 ?
The 1064 is BGA as far as I remember, so it is not trivial to assemble.

jnk0le:

--- Quote from: brucehoult on April 20, 2024, 05:38:08 am ---I very much doubt that a M7 can dual-issue FP instructions with other FP instructions. Two int, an int and an FP, something and a branch ... sure.

--- End quote ---
Only 1 FMA per cycle which can't even dual issue with FP loads


--- Quote from: brucehoult on April 20, 2024, 05:38:08 am ---I think the M7 is somewhat similar to the A53 (other than one being 32 bit and the other 64 of course) in averaging maybe 1.3 IPC on most code, unless it's very carefully hand-written. Newer designs with early&late ALUs in the 2nd pipe (A55, SiFive U74 etc) are more like 1.6 IPC.

--- End quote ---

CM7 does actually have early/late alu design (1 cycle apart, 1 cycle load to use), only AGU and shift, mov, add, sub instructions can use it (+skewed ones)
There are a lot of other things that can tank the IPC: https://github.com/jnk0le/random/tree/master/pipeline%20cycle%20test#cortex-m7

nimish:
Pragmatically I'd just go buy any easy to use RP2040 based board since the PIO can replace a lot of low level IO protocols and there's great software support.

But if you really want >500MHz you're likely stuck with M7 based parts or Cortex-R5

What exactly are you trying to do? The core matters much less than the peripherals

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