EEVblog Electronics Community Forum
Electronics => Microcontrollers => Topic started by: legacy on September 13, 2014, 02:32:06 pm
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hi guys
i have been studying this (http://www.fpga4fun.com/JTAG2.html) tutorial that shows a few details about the jtag tap.
(http://www.fpga4fun.com/images/JTAG_TAP.gif)
I have understood
- how to determine the IR register length
- how to read the IDcode (manufacture, revision, etc etc)
- hot to determine how many devices are in the jtag chain
i can't understand how to read a DR register without corrupting it!
the jtag tap seems to read/write at the same time, so if you go into Caputure-DR you make the TAP machine to copy a pointed (1) register content into "scan register", so you can read it with Shift-DR through TDI, but … every time you issue a Shift-DR you also write into scan register content, so when you go into Update-DR you are copying the register content back to the pointed register content
and here we go, getting a corruption :wtf:
do i miss something in the TAP behavior ? who can clarify with an example ?
thanks
(1) you can point registers with IR instructions, for example if IR is equal to b1110 then you are pointing the IDCode register (read only)
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That depends on an instruction you are issuing. Some instructions like IDCODE ignores Update-DR, some have a paired instruction to read data for future updates (SAMPLE can be used to get some default value for future INTEST/EXTEST). Or in the most general case you can shift in the same values you are shifting out: in Shift-DR state you see the first bit value on TDO before shifting in something on TDI - so just set TDI=TDO and clock out the next bit.
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imagine you have an Advance Debug Interface (aka ADI) connected to your jtag TAP machine, how could you ran the desk with its registers ?
does the tap need a pair of instructions (read, write) for each the ADI's registers ?
each read instruction will ignore the write-back phase in the update-Dr state
each write instruction will take the write-back phase in the update-Dr state
is it correct ?
example
the ADI unit has 4 registers {ADI.r0, ADI.r1, ADI.r2, ADI.r3}
does the jtag TAP machine need to have these custom instructions {{rd_ADI.r0, wr_ADI.r0}, {rd_ADI.r1, wr_ADI.r1}, {rd_ADI.r2, wr_ADI.r2}, rd_ADI.r3, wr_ADI.r3}} ?
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Why not? It should work.
But there are other ways also: for example, ARM debug unit (ICEBreaker) registers are accessed with a single IR instruction, but DR has address, r/w, data fields